WangXuan95 / FPGA-DDR-SDRAM
An FPGA-based AXI4 DDR1 controller. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。
☆147Updated last year
Related projects ⓘ
Alternatives and complementary repositories for FPGA-DDR-SDRAM
- This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调…☆116Updated last year
- Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline v…☆141Updated last year
- ☆51Updated last year
- A SATA host (HBA) core based on Xilinx FPGA with GTH to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器，用来读写硬盘。☆85Updated last year
- An FPGA-based MII to RMII & SMII converter to connect 100M ethernet PHY chip such as LAN8720 or KSZ8041TLI-S. 基于FPGA的MII转RMII和MII转SMII，用来…☆78Updated last year
- An FPGA-based PNG image decoder, which can extract original pixels from PNG files. 基于FPGA的PNG图像解码器，可以从PNG文件中解码出原始像素。☆88Updated last year
- Verilog implementation of SHA1/SHA224/SHA256/SHA384/SHA512. 使用Verilog实现的SHA1/SHA224/SHA256/SHA384/SHA512计算器。☆61Updated last year
- 使用 Vivado+PetaLinux 为 Xilinx Zynq7 搭建 Linux 系统 —— 以 Zedboard 为例☆89Updated 2 months ago
- An FPGA-based LZMA compressor for generic data compression. 基于FPGA的LZMA压缩器，用于通用数据压缩。☆74Updated last year
- An FPGA-based high performance MPEG2 encoder for video compression. 基于FPGA的高性能MPEG2视频编码器，可实现视频压缩。☆116Updated 9 months ago
- An FPGA-based Ultra-High Throughput JPEG-LS encoder, which provides lossless image compression. 一个超高性能的FPGA JPEG-LS编码器，用来进行无损图像压缩。☆89Updated 2 months ago
- Imitate SDcard using FPGAs. 使用FPGA模拟和伪装SD卡。☆105Updated last year
- An FPGA-based GZIP (deflate) compressor, which input raw data and output standard GZIP format (as known as .gz file format). 基于FPGA的GZIP压…☆100Updated last year
- An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。☆267Updated last year
- An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。☆228Updated last year
- An implementation of JPEG-LS extension (ITU-T T.870).☆31Updated last month
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆107Updated 2 years ago
- 这是我所开发的两个项目，包括ov5640-ddr3-usb2.0高速图像采集系统以及NOIP1SN1300A-ddr3-sdhc高速地表图像采集及存储系统☆81Updated 7 years ago
- asynchronous FIFO that support Non-symmetric aspect ratios(different read and write data widths), First-Word Fall-Through and data counte…☆13Updated last year
- 视频旋转（2019FPGA大赛）☆29Updated 4 years ago
- AXI协议规范中文翻译版☆132Updated 2 years ago
- SDRAM controller with AXI4 interface☆78Updated 5 years ago
- An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码…☆211Updated 2 months ago
- Step by step tutorial for building CortexM0 SoC☆35Updated 2 years ago
- Cortex M0 based SoC☆70Updated 3 years ago
- AXI总线连接器☆91Updated 4 years ago
- ☆34Updated 9 years ago
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆67Updated 3 years ago
- FFT implement by verilog_测试验证已通过☆52Updated 8 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆111Updated 3 years ago