WangXuan95 / FPGA-DDR-SDRAMView external linksLinks
An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。
☆202Sep 15, 2023Updated 2 years ago
Alternatives and similar repositories for FPGA-DDR-SDRAM
Users that are interested in FPGA-DDR-SDRAM are comparing it to the libraries listed below
Sorting:
- An FPGA-based PNG image decoder, which can extract original pixels from PNG files. 基于FPGA的PNG图像解码 器，可以从PNG文件中解码出原始像素。☆103Sep 14, 2023Updated 2 years ago
- Verilog implementation of SHA1/SHA224/SHA256/SHA384/SHA512. 使用Verilog实现的SHA1/SHA224/SHA256/SHA384/SHA512计算器。☆78Sep 14, 2023Updated 2 years ago
- An FPGA-based SD-card reader via SPI bus, which can read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器(通过SPI总线)，可以从FAT16或FA…☆95Sep 14, 2023Updated 2 years ago
- An FPGA-based LZMA compressor for generic data compression. 基于FPGA的LZMA压缩器，用于通用数据压缩。☆90Sep 14, 2023Updated 2 years ago
- An FPGA-based MII to RMII & SMII converter to connect 100M ethernet PHY chip such as LAN8720 or KSZ8041TLI-S. 基于FPGA的MII转RMII和MII转SMII，用来…☆99Sep 14, 2023Updated 2 years ago
- An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。☆334Sep 15, 2023Updated 2 years ago
- Imitate SDcard using FPGAs. 使用FPGA模拟伪装SD卡。☆133Sep 14, 2023Updated 2 years ago
- A SATA host (HBA) core based on Xilinx FPGA with GTH to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器，用来读写硬盘。☆134Sep 14, 2023Updated 2 years ago
- 一个FPGA核心板设计，体积小、低成本、易用、扩展性强。☆91Sep 14, 2023Updated 2 years ago
- An FPGA-based NFC (RFID) reader with a simple circuit rather than RFID chips. 用FPGA+分立器件电路搭建一个NFC(RFID)读卡器，不需要专门的RFID芯片。☆142Jan 26, 2024Updated 2 years ago
- C# 软键盘输入框，包括9键和26键，可用于触屏☆25Apr 21, 2022Updated 3 years ago
- This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调…☆295Sep 14, 2023Updated 2 years ago
- An FPGA-based Ultra-High Throughput JPEG-LS encoder, which provides lossless image compression. 一个超高性能的FPGA JPEG-LS编码器，用来进行无损图像压缩。☆102Sep 18, 2024Updated last year
- Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline v…☆224Sep 14, 2023Updated 2 years ago
- 使用 Vivado+PetaLinux 为 Xilinx Zynq7 搭建 Linux 系统 —— 以 Zedboard 为例☆118Sep 19, 2024Updated last year
- An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码…☆306Sep 18, 2024Updated last year
- An FPGA-based MPEG2 encoder for video compression (1920x1080 120fps). 基于FPGA的MPEG2视频编码器，可实现视频压缩。☆142Jan 26, 2024Updated 2 years ago
- An FPGA-based FT232H/FT600 chip controller for rapid data transmission via USB. 使用FT232H/FT600芯片进行FPGA与电脑之间的高速数据传输。☆329May 21, 2024Updated last year
- An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。☆330Sep 14, 2023Updated 2 years ago
- ☆66Mar 14, 2023Updated 2 years ago
- An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA comm…☆862Dec 6, 2024Updated last year
- An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。☆428Sep 14, 2023Updated 2 years ago
- An implementation of JPEG-LS extension (ITU-T T.870).☆33Jun 2, 2025Updated 8 months ago
- 一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。☆602Sep 15, 2023Updated 2 years ago
- An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …☆150Sep 15, 2023Updated 2 years ago
- A lightweight image converter which supports PNG, PNM, BMP, QOI, JPEG-LS, and H.265 intra-frame.☆57Jun 7, 2025Updated 8 months ago
- An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。☆840Sep 15, 2023Updated 2 years ago
- Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核☆776Sep 14, 2023Updated 2 years ago
- TinyZZZ includes GZIP, LZ4, ZSTD, LZMA compression algorithms written in C language, unlike the official code, this code mainly focuses o…☆72Jul 25, 2025Updated 6 months ago
- Wishbone SATA Controller☆24Oct 16, 2025Updated 3 months ago
- A DDR3 memory controller in Verilog for various FPGAs☆560Oct 10, 2021Updated 4 years ago
- DDR2 memory controller written in Verilog☆82Feb 28, 2012Updated 13 years ago
- SDRAM controller with AXI4 interface☆101Aug 8, 2019Updated 6 years ago
- SDRAM controller with multiple wishbone slave ports☆30Oct 26, 2018Updated 7 years ago
- An FPGA-based QOI image compressor and decompressor in Verilog. 基于FPGA的QOI图像压缩器和解压器。☆39Sep 18, 2024Updated last year
- Verilog HDL implementation of SDRAM controller and SDRAM model☆40Jun 19, 2024Updated last year
- 【例程】国产高云FPGA 开发板及其工程☆43Feb 2, 2026Updated last week
- UART -> AXI Bridge☆71Jul 1, 2021Updated 4 years ago
- 学习AXI接口，以及xilinx DDR3 IP使用☆40Mar 6, 2017Updated 8 years ago