Alternatives and similar repositories for 10G_EthernetMAC_SystemVerilog_OOP

Users that are interested in 10G_EthernetMAC_SystemVerilog_OOP are comparing it to the libraries listed below

• mgtm98 / pcie5_phy
  PCIE 5.0 Graduation project (Verification Team)
  ☆78Updated last year
• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆68Updated 4 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆51Updated 3 years ago
• kkenshin1 / AXI-Ethernet-UVM
  A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM
  ☆25Updated 3 years ago
• wenxuan-hu / SSRL_work
  work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework
  ☆34Updated 2 years ago
• andres-mancera / ethernet_10ge_mac_SV_UVM_tb
  SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
  ☆145Updated 7 years ago
• Travissss / ahb2apb-bridge
  An uvm verification env for ahb2apb bridge
  ☆54Updated 4 years ago
• Siddhi-95 / AHB-to-APB-Bridge-Verification
  Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.
  ☆95Updated 2 years ago
• muguang123 / AXI_Verification
  Verification AXI-4 bus standard using UVM and System Verilog
  ☆15Updated 7 years ago
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆128Updated 4 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆31Updated 6 years ago
• gupta409 / Processor-UVM-Verification
  System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
  ☆105Updated 7 months ago
• muneebullashariff / i2c_vip
  Verification IP for I2C protocol
  ☆46Updated 3 years ago
• marcoz001 / axi-uvm
  yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
  ☆122Updated 7 years ago
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆44Updated 5 years ago
• kdurant / axi-ddr3
  学习AXI接口，以及xilinx DDR3 IP使用
  ☆37Updated 8 years ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆42Updated 3 years ago
• Anjali-287 / SPI-Interface
  UVM Testbench to verify serial transmission of data between SPI master and slave
  ☆48Updated 5 years ago
• dadongshangu / async_FIFO
  This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…
  ☆64Updated last year
• wanderingnail / AXI_DMA
  ☆20Updated 2 years ago
• akzare / Async_FIFO_Verification
  Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.
  ☆53Updated 4 years ago
• Verdvana / AXI_SRAM
  支持AXI总线协议的8k×8 SP SRAM
  ☆25Updated 5 years ago
• nelsoncsc / ISP_UVM
  A Framework for Design and Verification of Image Processing Applications using UVM
  ☆104Updated 7 years ago
• letitbe0201 / AXI-DMA-master-verification
  ☆26Updated 4 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆105Updated 4 years ago
• brown9804 / PCIe-Physical-Layer
  Implementation of the PCIe physical layer
  ☆47Updated 3 weeks ago
• ptracton / AXI_BFM
  AXI4 BFM in Verilog
  ☆32Updated 8 years ago
• DexWen / FFT_Verilog
  FFT implement by verilog_测试验证已通过
  ☆58Updated 8 years ago
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆39Updated 2 years ago
• visky2096 / AHB-to-I2C
  Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…
  ☆22Updated 6 years ago