aquaxis/gemac external links

---

GitHub - View repository

GitHub.dev - Open in online code editor

Star history - Growth chart over time

deps.dev - Dependencies and security vulnerabilities

Gitingest - Export source code for LLM usage

Repomix - Export source code for LLM usage

uithub - Export source code for LLM usage

Close

aquaxis/gemac

Readme badge preview -

If you own this repo, copy the snippet below and add it to your README.md

---

Copy

[![RelatedRepos](https://img.shields.io/badge/related-repos-yellow)](https://relatedrepos.com/gh/aquaxis/gemac)

Close

aquaxis / gemacView on GitHubMore

• External links
• Readme badge

Gigabit MAC + UDP/TCP/IP offload Engine

☆35Sep 17, 2019Updated 6 years ago

Alternatives and similar repositories for gemac

Users that are interested in gemac are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.

• akzare / HardORB

  View on GitHub
  TCP/IP and UDP/IP protocol stack off-loading
  ☆19Aug 9, 2020Updated 5 years ago
• hpb-project / TOE

  View on GitHub
  TCP Offload Engine
  ☆78Nov 18, 2017Updated 8 years ago
• aquaxis / aq_mipi_csi2rx_ultrascaleplus

  View on GitHub
  ☆34Nov 26, 2019Updated 6 years ago
• freecores / mac_layer_switch

  View on GitHub
  100 MB/s Ethernet MAC Layer Switch
  ☆15Jul 17, 2014Updated 11 years ago
• KutuSystems / XilinxIP

  View on GitHub
  Xilinx IP repository
  ☆13May 5, 2018Updated 8 years ago
• GPU virtual machines on DigitalOcean Gradient AI • Ad
  Get to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
• freecores / nova

  View on GitHub
  H.264/AVC Baseline Decoder
  ☆16Jul 17, 2014Updated 11 years ago
• fpgadeveloper / ethernet-fmc-axi-eth

  View on GitHub
  Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks
  ☆72Updated this week
• circuitvalley / Cypress-FX3-USB3

  View on GitHub
  Project related to Cypress FX3 USB 3.0 Controller published on
  ☆17Dec 2, 2019Updated 6 years ago
• ZipCPU / wbsata

  View on GitHub
  Wishbone SATA Controller
  ☆26Jun 23, 2026Updated last week
• C-L-G / video_timing_generator

  View on GitHub
  标准视频时序生成器
  ☆10Feb 9, 2020Updated 6 years ago
• marph91 / pico-png

  View on GitHub
  PNG encoder, implemented in VHDL
  ☆23Mar 30, 2024Updated 2 years ago
• Essenceia / Nasdaq-HFT-FPGA

  View on GitHub
  RTL design for a nasdaq compatible high frequency trading low level. Supports itch on moldudp64.
  ☆103Dec 24, 2023Updated 2 years ago
• Digilent / vivado-hierarchies

  View on GitHub
  ☆17Aug 18, 2020Updated 5 years ago
• opensmartnic / panic_with_cocotb

  View on GitHub
  ☆14May 15, 2023Updated 3 years ago
• Deploy on Railway without the complexity - Free Credits Offer • Ad
  Connect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
• ultraembedded / core_usb_bridge

  View on GitHub
  USB -> AXI Debug Bridge
  ☆44Jun 5, 2021Updated 5 years ago
• kdurant / axi-ddr3

  View on GitHub
  学习AXI接口，以及xilinx DDR3 IP使用
  ☆40Mar 6, 2017Updated 9 years ago
• ntpt7921 / Verilog_UDP_TCP

  View on GitHub
  Module giải mã và đóng gói cho các giao thức IP/TCP+UDP. Viết bằng Verilog. Đề tài thực hiện cho Đồ án thiết kế luận lý.
  ☆13Jan 3, 2022Updated 4 years ago
• hpcn-uam / 100G-fpga-network-stack-core

  View on GitHub
  This repo contains the Limago code
  ☆93May 8, 2025Updated last year
• stevenbell / csirx

  View on GitHub
  Open-source CSI-2 receiver for Xilinx UltraScale parts
  ☆37Jul 10, 2019Updated 6 years ago
• hpcn-uam / Limago

  View on GitHub
  Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack
  ☆138Sep 11, 2021Updated 4 years ago
• bmartini / verilog-arbiter

  View on GitHub
  A look ahead, round-robing parametrized arbiter written in Verilog.
  ☆43May 22, 2020Updated 6 years ago
• Cognoscan / AxiCores

  View on GitHub
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆17Mar 14, 2020Updated 6 years ago
• maxs-well / Ethernet-design-verilog

  View on GitHub
  Gigabit Ethernet UDP communication driver
  ☆85Jul 26, 2019Updated 6 years ago
• Bare Metal GPUs on DigitalOcean Gradient AI • Ad
  Purpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
• fpgasystems / fpga-network-stack

  View on GitHub
  Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)
  ☆935Apr 15, 2026Updated 2 months ago
• steveicarus / simbus

  View on GitHub
  Icarus SIMBUS
  ☆21Nov 6, 2019Updated 6 years ago
• iscgar / uart-server

  View on GitHub
  A simple program that serves a serial port over TCP
  ☆12Nov 8, 2018Updated 7 years ago
• fengcanyue / MotorMeasurement

  View on GitHub
  电机转速转矩测量系统分两部分：1.基于STM32F103单片机的信号采集模块。2、用Qt编写的界面显示软件
  ☆12Jun 28, 2016Updated 10 years ago
• chu11 / freeipmi-mirror

  View on GitHub
  Mirror of GNU FreeIPMI Git Repo - http://savannah.gnu.org/projects/freeipmi/. I maintain the upstream of FreeIPMI and can accept Github …
  ☆13Jun 15, 2026Updated 2 weeks ago
• qmor / elcus-1553-driver-linux

  View on GitHub
  ☆12Dec 28, 2022Updated 3 years ago
• freecores / udp_ip_stack

  View on GitHub
  1G eth UDP / IP Stack
  ☆10Jul 17, 2014Updated 11 years ago
• Elphel / x393

  View on GitHub
  mirror of https://git.elphel.com/Elphel/x393
  ☆41Mar 16, 2023Updated 3 years ago
• marsohod4you / Amber-Marsohod2

  View on GitHub
  Port of Amber ARM Core project to Marsohod2 platform
  ☆13Dec 4, 2019Updated 6 years ago
• Deploy on Railway without the complexity - Free Credits Offer • Ad
  Connect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
• wtiandong / Hardware_circular_buffer_controller

  View on GitHub
  This is a circular buffer controller used in FPGA.
  ☆35Jan 12, 2016Updated 10 years ago
• wicker / SystemVerilog-Constructs

  View on GitHub
  Examples of unions, interfaces, and assertions in SystemVerilog
  ☆13Aug 31, 2013Updated 12 years ago
• RISCV-on-Microsemi-FPGA / CPUs

  View on GitHub
  CPUs
  ☆17Dec 21, 2020Updated 5 years ago
• ultraembedded / core_spiflash

  View on GitHub
  SPI-Flash XIP Interface (Verilog)
  ☆50Oct 24, 2021Updated 4 years ago
• Archit-halder / Viterbi-Algorithm

  View on GitHub
  This is about the implementation of (2,1,4) Convolutional Encoder and Viterbi Decoder using Verilog VHDL.
  ☆14Aug 12, 2020Updated 5 years ago
• kailashnath / OpenAFDX

  View on GitHub
  This project intends to develop tools around AFDX. (Avionics Full Duplex Switched Ethernet).
  ☆10Oct 27, 2010Updated 15 years ago
• xuelanglv / RocketGroundStation

  View on GitHub
  使用KCF目标追踪算法进行目标识别和追踪，实现导弹的精确打击。
  ☆10Jan 28, 2019Updated 7 years ago