aquaxis / gemac

Related projects: ⓘ

• brown9804 / PCIe_physical_layer
  Implementation of the PCIe physical layer
  ☆28Updated 4 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆53Updated 4 years ago
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆41Updated 3 years ago
• lewiz-support / LMAC_CORE3
  Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps
  ☆37Updated last year
• bmartini / verilog-arbiter
  A look ahead, round-robing parametrized arbiter written in Verilog.
  ☆40Updated 4 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆27Updated 5 years ago
• kdurant / axi-ddr3
  学习AXI接口，以及xilinx DDR3 IP使用
  ☆34Updated 7 years ago
• pulp-platform / axi_spi_master
  ☆19Updated 4 years ago
• freecores / xge_mac
  Ethernet 10GE MAC
  ☆44Updated 10 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆44Updated 4 months ago
• govindjeevan / Weighted-Round-Robin-Arbiter
  Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components
  ☆18Updated 6 years ago
• alexforencich / cocotbext-eth
  Ethernet interface modules for Cocotb
  ☆53Updated 10 months ago
• muzafferkal / axi-bfm
  AXI3 Bus Functional Models (Initiator & Target)
  ☆26Updated last year
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆66Updated 6 years ago
• andres-mancera / ethernet_10ge_mac_SV_tb
  SystemVerilog testbench for an Ethernet 10GE MAC core
  ☆42Updated 8 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆52Updated 3 years ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆31Updated 2 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆48Updated 10 years ago
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆100Updated 2 years ago
• ptracton / AXI_BFM
  AXI4 BFM in Verilog
  ☆32Updated 7 years ago
• rgwan / AMBA
  Collection of IPs based on AMBA (AHB, APB, AXI) protocols
  ☆20Updated 7 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆75Updated 4 years ago
• wanderingnail / AXI_DMA
  ☆14Updated last year
• antmicro / nvme-verilog-pcie
  ☆43Updated 2 years ago
• jerralph / riscv-vip
  For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
  ☆53Updated 3 years ago
• RoaLogic / ahb3lite_apb_bridge
  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
  ☆40Updated 4 months ago
• amiq-consulting / physical_coding_library
  ☆18Updated 8 years ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆49Updated 4 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆47Updated 3 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆82Updated 3 years ago