alibaba / vector-accelerating-unitLinks
vector accelerating unit
☆34Updated 4 years ago
Alternatives and similar repositories for vector-accelerating-unit
Users that are interested in vector-accelerating-unit are comparing it to the libraries listed below
Sorting:
- eyeriss-chisel3☆41Updated 3 years ago
- HLS for Networks-on-Chip☆35Updated 4 years ago
- ☆17Updated 3 months ago
- ☆32Updated 3 months ago
- Ratatoskr NoC Simulator☆27Updated 4 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆56Updated 10 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆58Updated last month
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆58Updated last week
- ☆65Updated 6 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- ☆72Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated 11 months ago
- A systolic array matrix multiplier☆24Updated 5 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆198Updated 5 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆83Updated last year
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- Hardware accelerator for convolutional neural networks☆49Updated 3 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆104Updated 4 years ago
- ☆53Updated 6 years ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆150Updated this week
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated 2 weeks ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- ☆34Updated 6 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆41Updated 2 years ago
- An Open-Source Tool for CGRA Accelerators☆67Updated 4 months ago
- ☆27Updated 5 years ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆40Updated 2 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.