alibaba / vector-accelerating-unit
vector accelerating unit
☆25Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for vector-accelerating-unit
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆19Updated last year
- ☆10Updated 5 months ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆42Updated 2 years ago
- cycle accurate Network-on-Chip Simulator☆25Updated last year
- ☆22Updated 5 years ago
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆10Updated 4 years ago
- ☆32Updated 5 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆12Updated 4 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆65Updated 3 years ago
- ☆70Updated last year
- ☆18Updated last year
- ☆33Updated 3 years ago
- HLS for Networks-on-Chip☆31Updated 3 years ago
- A systolic array matrix multiplier☆23Updated 5 years ago
- eyeriss-chisel3☆39Updated 2 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆31Updated last year
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆40Updated this week
- ☆21Updated last month
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆23Updated last month
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆46Updated 7 years ago
- Ratatoskr NoC Simulator☆21Updated 3 years ago
- CNN Accelerator in Frequency Domain☆10Updated 4 years ago
- NPUsim: Full-system, Cycle-accurate, Value-aware NPU Simulator☆24Updated last week
- DMA controller for CNN accelerator☆12Updated 7 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆59Updated 3 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆17Updated 11 months ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆24Updated 4 years ago
- Project repo for the POSH on-chip network generator☆43Updated last year
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.☆16Updated 7 months ago