alibaba / vector-accelerating-unitLinks
vector accelerating unit
☆35Updated 5 years ago
Alternatives and similar repositories for vector-accelerating-unit
Users that are interested in vector-accelerating-unit are comparing it to the libraries listed below
Sorting:
- ☆37Updated 2 months ago
- eyeriss-chisel3☆40Updated 3 years ago
- ☆19Updated 7 months ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆76Updated last month
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆83Updated 4 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 6 months ago
- A systolic array matrix multiplier☆30Updated 6 years ago
- HLS for Networks-on-Chip☆39Updated 4 years ago
- An integrated CGRA design framework☆91Updated 9 months ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- ☆61Updated 8 months ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆50Updated 10 months ago
- ☆79Updated 11 years ago
- Public release☆58Updated 6 years ago
- RTL implementation of Flex-DPE.☆115Updated 5 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆74Updated 2 months ago
- ☆71Updated 7 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- ☆40Updated 6 years ago
- ☆28Updated 6 years ago
- FSA: Fusing FlashAttention within a Single Systolic Array☆82Updated 4 months ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆74Updated 6 years ago
- Ratatoskr NoC Simulator☆29Updated 4 years ago
- Template for project1 TPU☆21Updated 4 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Updated 3 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆149Updated this week
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- An Open-Source Tool for CGRA Accelerators☆81Updated 3 months ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆36Updated 2 years ago
- An open-source UCIe controller implementation☆81Updated this week