coleblackman / TIDENetLinks
TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google SkyWater PDK, OpenLANE, and Caravel.
☆17Updated 2 years ago
Alternatives and similar repositories for TIDENet
Users that are interested in TIDENet are comparing it to the libraries listed below
Sorting:
- ☆27Updated 6 years ago
- A RRAM addon for the NCSU FreePDK 45nm☆24Updated 3 years ago
- SRAM☆22Updated 5 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Updated 3 years ago
- FPU Generator☆20Updated 4 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 4 years ago
- An open source PDK using TIGFET 10nm devices.☆51Updated 2 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 3 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆64Updated 2 weeks ago
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆14Updated 5 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆20Updated 2 weeks ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆27Updated 3 weeks ago
- CNN accelerator☆27Updated 8 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Updated 12 years ago
- ☆30Updated 2 weeks ago
- sram/rram/mram.. compiler☆42Updated 2 years ago
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆10Updated 5 years ago
- Ratatoskr NoC Simulator☆28Updated 4 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆26Updated last week
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆22Updated 10 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated 5 months ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- ☆18Updated last month
- MathLib DAC 2023 version☆12Updated 2 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆32Updated 3 years ago
- LIS Network-on-Chip Implementation☆31Updated 9 years ago
- A configurable SRAM generator☆56Updated 2 months ago