TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google SkyWater PDK, OpenLANE, and Caravel.
☆18Jan 30, 2023Updated 3 years ago
Alternatives and similar repositories for TIDENet
Users that are interested in TIDENet are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This is the Google/EFabless/Skywater Caravel submission of an Analog Spiking Neuron Circuit. The submission also includes a SONOS transis…☆12Apr 21, 2023Updated 3 years ago
- A linux PCIe driver for Altera☆11Oct 9, 2018Updated 7 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆11Jan 27, 2022Updated 4 years ago
- 🐆 A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration for *AdderNet*☆22May 27, 2024Updated 2 years ago
- SoC for muntjac☆14Jun 18, 2025Updated last year
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆47Jul 28, 2017Updated 9 years ago
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆13May 26, 2016Updated 10 years ago
- Processing in Memory Emulation☆31Feb 24, 2023Updated 3 years ago
- Symbolic differentation of algebraic expressions with Python and Tcl interfaces.☆20Aug 14, 2026Updated last month
- FPU Generator☆21Updated this week
- Arrow Matrix Decomposition - Communication-Efficient Distributed Sparse Matrix Multiplication☆15Mar 25, 2024Updated 2 years ago
- ☆13May 10, 2018Updated 8 years ago
- OpenTitan FI formal verification framework☆18Aug 29, 2023Updated 3 years ago
- An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop…☆16Jul 22, 2020Updated 6 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Convolution Neural Network of vgg19 model in verilog☆50Jan 4, 2018Updated 8 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆21Feb 28, 2021Updated 5 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆83Dec 11, 2023Updated 2 years ago
- System on Chip toolkit for nMigen☆19Apr 29, 2020Updated 6 years ago
- ☆22Aug 6, 2026Updated 2 months ago
- ☆10Aug 22, 2023Updated 3 years ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆58Jun 12, 2021Updated 5 years ago
- Pytorch implementation of SEENN (Spiking Early Exit Neural Networks) (NeurIPS 2023)☆19Nov 18, 2024Updated last year
- ☆14Aug 8, 2022Updated 4 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- NeuraChip Accelerator Simulator☆17Apr 26, 2024Updated 2 years ago
- RISC-V Configuration Structure☆41Oct 30, 2024Updated last year
- Hardware Implementation of Sigmoid Function using verilog HDL☆16Dec 16, 2019Updated 6 years ago
- A DSL for Linear Temporal Logic + Interface with Z3 for solving☆11Mar 12, 2015Updated 11 years ago
- A 4x4 Weight Stationary Systolic Array Implementation☆15Oct 16, 2023Updated 2 years ago
- ☆17Mar 18, 2025Updated last year
- System Verilog code describing a fully combinational binarized neural network.☆36Jul 6, 2018Updated 8 years ago
- We open-source our layout level fast EM simulation tool, EMSim, to the public.☆16Feb 8, 2024Updated 2 years ago
- Multi Layer Perceptron by Vivado HLS for Xilinx FPGA implementation☆12Dec 26, 2016Updated 9 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Analog and power building blocks for sky130 pdk☆22Mar 3, 2021Updated 5 years ago
- a hardware task scheduler design☆10Sep 14, 2022Updated 4 years ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆155Mar 17, 2023Updated 3 years ago
- A Full-System Simulator for CXL-Based SSD Memory System☆47Dec 24, 2024Updated last year
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆24Aug 10, 2018Updated 8 years ago
- NeuroSpector: Dataflow and Mapping Optimizer for Deep Neural Network Accelerators☆23Mar 20, 2025Updated last year
- the released codes for DiamondGAN - a scalable multiple-to-one domain translation approach in medical imaging☆12Jan 16, 2020Updated 6 years ago