coleblackman / TIDENetLinks
TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google SkyWater PDK, OpenLANE, and Caravel.
☆17Updated 2 years ago
Alternatives and similar repositories for TIDENet
Users that are interested in TIDENet are comparing it to the libraries listed below
Sorting:
- ☆28Updated 6 years ago
- A RRAM addon for the NCSU FreePDK 45nm☆24Updated 3 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Updated 3 years ago
- Approximate arithmetic circuits for FPGAs☆11Updated 5 years ago
- SRAM☆22Updated 5 years ago
- FPU Generator☆20Updated 4 years ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Updated 12 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 4 years ago
- Ratatoskr NoC Simulator☆28Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆66Updated 3 weeks ago
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆11Updated 5 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆20Updated last week
- Reconfigurable Binary Engine☆17Updated 4 years ago
- Open source process design kit for 28nm open process☆67Updated last year
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆15Updated 11 years ago
- An open source PDK using TIGFET 10nm devices.☆54Updated 2 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆17Updated last year
- CNN accelerator☆27Updated 8 years ago
- sram/rram/mram.. compiler☆43Updated 2 years ago
- Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆29Updated 8 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Template for project1 TPU☆19Updated 4 years ago
- Project repo for the POSH on-chip network generator☆52Updated 8 months ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆27Updated 6 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Updated 2 years ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆25Updated 6 years ago
- ☆32Updated this week
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆13Updated 9 years ago