coleblackman / TIDENet
TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google SkyWater PDK, OpenLANE, and Caravel.
☆17Updated 2 years ago
Alternatives and similar repositories for TIDENet:
Users that are interested in TIDENet are comparing it to the libraries listed below
- ☆26Updated 5 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆40Updated 7 months ago
- SRAM☆22Updated 4 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 3 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆25Updated 4 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆18Updated 8 months ago
- A RRAM addon for the NCSU FreePDK 45nm☆23Updated 3 years ago
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆10Updated 4 years ago
- FPU Generator☆20Updated 3 years ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆26Updated 5 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆12Updated 5 years ago
- Open source RTL simulation acceleration on commodity hardware☆25Updated 2 years ago
- CNN accelerator☆27Updated 7 years ago
- Reconfigurable Binary Engine☆16Updated 4 years ago
- NoC based MPSoC☆10Updated 10 years ago
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆12Updated 4 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- Development of a Network on Chip Simulation using SystemC.☆31Updated 7 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- The Verilog source code for DRUM approximate multiplier.☆30Updated 2 years ago
- Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆27Updated last month
- RISC-V ISA based 32-bit processor written in HLS☆17Updated 5 years ago
- ☆27Updated 4 years ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- Neural Network accelerator powered by MVUs and RISC-V.☆13Updated 9 months ago
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 8 years ago
- ☆4Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- Open Source PHY v2☆28Updated last year