fabio-montagna / PULP-HDLinks
☆12Updated 7 years ago
Alternatives and similar repositories for PULP-HD
Users that are interested in PULP-HD are comparing it to the libraries listed below
Sorting:
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆52Updated 4 years ago
- ☆24Updated 2 years ago
- ☆18Updated last year
- ☆33Updated 6 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆36Updated 6 years ago
- Attentionlego☆12Updated last year
- Fast Emulation of Approximate DNN Accelerators in PyTorch☆23Updated last year
- ☆18Updated 2 years ago
- ☆10Updated 3 months ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆71Updated last year
- LoAS: Fully Temporal-Parallel Dataflow for Dual-Sparse Spiking Neural Networks, MICRO 2024.☆11Updated 4 months ago
- Collection of kernel accelerators optimised for LLM execution☆19Updated 3 months ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network☆43Updated 4 years ago
- ☆36Updated 4 months ago
- Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration☆23Updated 3 years ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆34Updated 5 years ago
- ☆27Updated 3 months ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆30Updated 6 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆34Updated 3 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆81Updated last year
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆72Updated 4 months ago
- ☆12Updated last year
- [FPGA-2022] N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores☆12Updated 3 years ago
- ☆35Updated 5 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆58Updated 3 years ago
- ☆25Updated last year
- ☆72Updated 2 years ago