fabio-montagna / PULP-HD

Related projects ⓘ

Alternatives and complementary repositories for PULP-HD

• sharc-lab / gnn-builder
  An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization
  ☆19Updated this week
• walkieq / RNN_HLS
  An LSTM template and a few examples using Vivado HLS
  ☆42Updated 6 months ago
• Accelergy-Project / processing-in-memory-design
  ☆24Updated 6 months ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆59Updated 3 years ago
• AlexMontgomerie / fpgaconvnet-tutorial
  A collection of tutorials for the fpgaConvNet framework.
  ☆30Updated last month
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆51Updated 2 years ago
• hyoukjun / DesignCNNAccelerators
  Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017
  ☆25Updated 6 years ago
• DNN-Accelerators / Open-Source-IPs
  ☆32Updated 5 years ago
• Aayush-Ankit / puma-simulator
  [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…
  ☆55Updated last year
• dimdano / adapt
  Fast Emulation of Approximate DNN Accelerators in PyTorch
  ☆17Updated 8 months ago
• yonseicasl / NPUsim
  NPUsim: Full-system, Cycle-accurate, Value-aware NPU Simulator
  ☆18Updated this week
• MartaAndronic / PolyLUT
  PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…
  ☆39Updated 9 months ago
• neurosim / DNN_NeuroSim_V2.0
  Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)
  ☆45Updated 3 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆44Updated 2 years ago
• CRAFT-THU / XB-Sim
  A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration
  ☆31Updated 2 years ago
• UCLA-VAST / CLINK
  Compact LSTM inference kernel (CLINK) designed in C/HLS for FPGA implementation.
  ☆17Updated 5 years ago
• maestro-project / gamma
  ☆33Updated 4 months ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆65Updated 3 years ago
• UCLA-VAST / FlexCNN
  ☆69Updated last year
• UCLA-VAST / hbmbench
  ☆23Updated 3 years ago
• template-hls / template-hls-float
  ☆27Updated 5 years ago
• arkhodamoradi / s2n2
  ☆16Updated 3 years ago
• SFU-HiAccel / uBench
  [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers
  ☆29Updated 2 years ago
• snagiri / CSE237D-PYNQ-SNN-Accelerator
  Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board
  ☆28Updated 5 years ago
• lizardll / ScalaBFS
  A Scalable BFS Accelerator on FPGA-HBM Platform
  ☆13Updated 3 years ago
• AlexMontgomerie / samo
  SAMO: Streaming Architecture Mapping Optimisation
  ☆32Updated last year
• UCLA-VAST / Serpens
  Serpens is an HBM FPGA accelerator for SpMV
  ☆14Updated 3 months ago
• adam-smnk / Open-CIM-Compiler
  ☆26Updated 3 years ago
• arc-research-lab / SSR
  SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)
  ☆26Updated 3 months ago
• gkrish19 / SIAM
  Scalable In-Memory Acceleration With Mesh: Device, Circuits, Architecture, and Algorithm
  ☆11Updated 4 years ago