Alternatives and similar repositories for PULP-HD

Users that are interested in PULP-HD are comparing it to the libraries listed below

• Accelergy-Project / processing-in-memory-design
  ☆26Updated last year
• DNN-Accelerators / Open-Source-IPs
  ☆33Updated 6 years ago
• booniebears / CoMN
  ☆15Updated last year
• sweetwenwen / Stochastic-computing-based-neural-network-accelerator
  ☆11Updated 5 years ago
• saunak1994 / CyNAPSEv11
  The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL
  ☆34Updated 5 years ago
• hyoukjun / DesignCNNAccelerators
  Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017
  ☆29Updated 6 years ago
• YulhwaKim / RRAMScalable_BNN
  Neural Network-Hardware Co-design for Scalable RRAM-based BNN Accelerators
  ☆11Updated 6 years ago
• neurosim / 3D_NeuroSim_V1.0
  Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration
  ☆22Updated 3 years ago
• CRAFT-THU / XB-Sim
  A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration
  ☆34Updated 3 years ago
• eardbi / hd-vhdl-library
  ☆10Updated 6 years ago
• zwhexplorer / Spiking-Neural-Network-Accelerator-EE552-project
  Spiking Neural Network Accelerator
  ☆15Updated 3 years ago
• elliothe / pytorx
  Neural Network Evaluation Tool on Crossbar-based Accelerator with Resistive Memory
  ☆40Updated 5 years ago
• Zhu-Zixuan / Bitlet-PE
  A bit-level sparsity-awared multiply-accumulate process element.
  ☆16Updated 11 months ago
• Intelligent-Microsystems-Lab / QuantizedLSTM
  Models and training scripts for "LSTMs for Keyword Spotting with ReRAM-based Compute-In-Memory Architectures" (ISCAS 2021).
  ☆15Updated 4 years ago
• arkhodamoradi / s2n2
  ☆17Updated 4 years ago
• adervay1 / CIMulator
  a Computing In Memory emULATOR framework
  ☆11Updated last year
• eda-lab / CNNAF-CNN-Accelerator
  CNN-Accelerator based on FPGA developed by verilog HDL.
  ☆10Updated 3 years ago
• neurosim / DNN_NeuroSim_V2.0
  Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)
  ☆48Updated 4 years ago
• eldrickm / wakey_wakey
  EE 272B - VLSI Design Project
  ☆12Updated 3 years ago
• DanielGerlinghoff / radix-encoding
  Framework for radix encoded SNN on FPGA
  ☆13Updated 3 years ago
• snagiri / CSE237D-PYNQ-SNN-Accelerator
  Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board
  ☆36Updated 5 years ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆77Updated 3 years ago
• KULeuven-MICAS / zigzag-imc
  HW accelerator mapping optimization framework for in-memory computing
  ☆24Updated this week
• sparsh0mittal / destiny_3d_cache
  Source code for DESTINY, a tool for modeling 2D and 3D caches designed with SRAM, eDRAM, STT-RAM, ReRAM and PCM. This is mirror of follow…
  ☆23Updated 5 months ago
• RuokaiYin / LoAS
  LoAS: Fully Temporal-Parallel Dataflow for Dual-Sparse Spiking Neural Networks, MICRO 2024.
  ☆11Updated 2 months ago
• neurosim / DNN_NeuroSim_V1.4
  Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)
  ☆68Updated 3 months ago
• dimdano / adapt
  Fast Emulation of Approximate DNN Accelerators in PyTorch
  ☆23Updated last year
• walkieq / RNN_HLS
  An LSTM template and a few examples using Vivado HLS
  ☆45Updated last year
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆45Updated 3 years ago
• KyleParkJong / Network-on-Chip-Simulator
  Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator
  ☆27Updated last year