fabio-montagna / PULP-HD
☆11Updated 7 years ago
Alternatives and similar repositories for PULP-HD
Users that are interested in PULP-HD are comparing it to the libraries listed below
Sorting:
- Framework for radix encoded SNN on FPGA☆12Updated 3 years ago
- Efficient single-pass hyperdimensional classifier. Mirror of https://gitlab.com/biaslab/onlinehd☆9Updated 4 years ago
- ☆17Updated 4 years ago
- ☆11Updated 5 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆36Updated 5 years ago
- ☆15Updated last year
- Hardware and software implementation of Sparsely-active SNNs☆14Updated 4 months ago
- ☆33Updated 6 years ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆33Updated 5 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆48Updated 3 years ago
- LoAS: Fully Temporal-Parallel Dataflow for Dual-Sparse Spiking Neural Networks, MICRO 2024.☆10Updated last month
- A Custom RISC-V Instruction Extension for SNN and CNN Computation☆14Updated 8 months ago
- Stochastic Computing for Deep Neural Networks☆33Updated 4 years ago
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆34Updated 2 years ago
- Spiking Neural Network Accelerator☆15Updated 3 years ago
- ☆18Updated 4 years ago
- ☆10Updated last month
- MINT, Multiplier-less INTeger Quantization for Energy Efficient Spiking Neural Networks, ASP-DAC 2024, Nominated for Best Paper Award☆13Updated last year
- An LSTM template and a few examples using Vivado HLS☆45Updated last year
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆17Updated last year
- Fast Emulation of Approximate DNN Accelerators in PyTorch☆22Updated last year
- ☆22Updated 2 years ago
- Code for paper "FuSeConv Fully Separable Convolutions for Fast Inference on Systolic Arrays" published at DATE 2021☆14Updated 3 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆10Updated 3 years ago
- ☆18Updated 2 years ago
- C++ code for HLS FPGA implementation of transformer☆16Updated 8 months ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆11Updated 4 years ago
- Neural Network Evaluation Tool on Crossbar-based Accelerator with Resistive Memory☆40Updated 5 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆77Updated 3 years ago