Alternatives and similar repositories for ZynqMP-ACP-Adapter

Users that are interested in ZynqMP-ACP-Adapter are comparing it to the libraries listed below

• pezy-computing / pzbcm
  Basic Common Modules
  ☆44Updated last month
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆121Updated 3 months ago
• SpinalHDL / SpinalCrypto
  SpinalHDL - Cryptography libraries
  ☆57Updated last year
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• mwrnd / innova2_experiments
  Works in Progress and Experiments for the Innova-2 Flex XCKU15P-based Board
  ☆17Updated last year
• johan92 / fpga-hash-table
  Simple hash table on Verilog (SystemVerilog)
  ☆50Updated 9 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆60Updated 2 years ago
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆125Updated 5 months ago
• DUNE / pl-nvme
  ☆36Updated 5 years ago
• ee-uet / UETRV-PCore
  Linux Capable 32-bit RISC-V based SoC in System Verilog
  ☆60Updated 11 months ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆66Updated last month
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆34Updated 8 months ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆37Updated last week
• pulp-platform / axi_spi_slave
  ☆27Updated 4 years ago
• Essenceia / ethernet-physical-layer
  RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.
  ☆30Updated last year
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆88Updated 3 months ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆61Updated last week
• k0nze / ultrazed_acp_example
  Tutorial on how to use the AXI ACP on the UltraZed-EG IOCC
  ☆11Updated 7 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆76Updated 2 months ago
• verilator / example-systemverilog
  ☆40Updated last year
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated last year
• b224hisl / rioschip
  ☆32Updated 2 years ago
• munetomo-maruyama / mmRISC-1
  RISC-V RV32IMAFC Core for MCU
  ☆39Updated 8 months ago
• pulp-platform / pulp-ethernet
  ☆14Updated 6 months ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆31Updated 9 years ago
• chipsalliance / fpga-interchange-schema
  ☆56Updated 3 years ago
• RSPwFPGAs / opae-xilinx
  OPAE porting to Xilinx FPGA devices.
  ☆39Updated 5 years ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆72Updated 5 years ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆85Updated 4 years ago
• RSPwFPGAs / qemu-hdl-cosim
  VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
  ☆49Updated 4 years ago