Alternatives and similar repositories for ZynqMP-ACP-Adapter

Users that are interested in ZynqMP-ACP-Adapter are comparing it to the libraries listed below

• pezy-computing / pzbcm
  Basic Common Modules
  ☆44Updated 2 months ago
• mwrnd / innova2_experiments
  Works in Progress and Experiments for the Innova-2 Flex XCKU15P-based Board
  ☆18Updated last year
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆34Updated 2 years ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆31Updated 9 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 4 months ago
• k0nze / ultrazed_acp_example
  Tutorial on how to use the AXI ACP on the UltraZed-EG IOCC
  ☆11Updated 7 years ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆70Updated this week
• Xilinx / pcie-model
  PCI Express controller model
  ☆68Updated 3 years ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆27Updated 2 years ago
• rdolbeau / VexRiscvBPluginGenerator
  ☆18Updated 3 years ago
• RSPwFPGAs / qemu-hdl-cosim
  VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
  ☆49Updated 4 years ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆37Updated last year
• beehive-lab / FastPath_MP
  FastPath_MP: An FPGA-based multi-path architecture for direct access from FPGA to NVMe SSD
  ☆36Updated 4 years ago
• chipsalliance / tilelink
  ☆35Updated 11 months ago
• b224hisl / rioschip
  ☆32Updated 2 years ago
• RSPwFPGAs / opae-xilinx
  OPAE porting to Xilinx FPGA devices.
  ☆39Updated 5 years ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated last week
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆122Updated 3 months ago
• antmicro / verilator-old-archived
  ☆22Updated 2 years ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆38Updated last week
• Cognoscan / AxiCores
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆16Updated 5 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆67Updated last year
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆125Updated 5 months ago
• hVHDL / hVHDL_floating_point
  high level VHDL floating point library for synthesis in fpga
  ☆18Updated this week
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆72Updated 5 years ago
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆44Updated 3 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆117Updated 3 years ago
• giuseppedongiovanni / nvme_comp_storage
  Computational Storage Device based on the open source project OpenSSD.
  ☆28Updated 5 years ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated last month
• yhqiu16 / NVMeCHA
  NVMe Controller featuring Hardware Acceleration
  ☆95Updated 4 years ago