Alternatives and similar repositories for ZynqMP-ACP-Adapter

Users that are interested in ZynqMP-ACP-Adapter are comparing it to the libraries listed below

• pezy-computing / pzbcm
  Basic Common Modules
  ☆46Updated last month
• thiemchu / rvcorep
  ☆10Updated 3 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆124Updated 6 months ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆54Updated last week
• k0nze / ultrazed_acp_example
  Tutorial on how to use the AXI ACP on the UltraZed-EG IOCC
  ☆11Updated 7 years ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆72Updated 6 years ago
• hVHDL / hVHDL_floating_point
  high level VHDL floating point library for synthesis in fpga
  ☆18Updated last month
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆34Updated 11 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆77Updated 6 months ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆121Updated 4 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 6 months ago
• Cognoscan / AxiCores
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆17Updated 5 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆70Updated last year
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆32Updated last year
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆63Updated last month
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆77Updated last month
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆53Updated 6 years ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆94Updated 3 months ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆61Updated 3 years ago
• dalance / svls-vscode
  SystemVerilog language server client for Visual Studio Code
  ☆23Updated 3 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆117Updated 3 years ago
• alexforencich / cocotb-test
  Unit testing for cocotb
  ☆11Updated 2 years ago
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆34Updated 2 years ago
• b224hisl / rioschip
  ☆33Updated 3 years ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆88Updated 4 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• mwrnd / innova2_experiments
  Works in Progress and Experiments for the Innova-2 Flex XCKU15P-based Board
  ☆18Updated last year
• egk696 / an-ethernet-controller
  A lightweight Ethernet MAC Controller IP for FPGA prototyping
  ☆14Updated 5 years ago
• aignacio / mpsoc_example
  ☆60Updated 4 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆51Updated 9 months ago