microsoft / DUA
DUA, is a communication architecture that provides uniform access for FPGA to data center resources. Without being limited by machine boundaries, DUA provides global names and a common interface for communicating across various resources, the underlying network automatically routing traffic and managing resource multiplexing.
☆38Updated 2 years ago
Alternatives and similar repositories for DUA:
Users that are interested in DUA are comparing it to the libraries listed below
- ☆59Updated 6 months ago
- PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing☆102Updated last year
- P4 compatible HLS modules☆10Updated 6 years ago
- Clio, ASPLOS'22.☆71Updated 2 years ago
- An Agile Chisel-Based SoC Design Framework☆26Updated 3 years ago
- ☆33Updated 3 years ago
- Modifications to GEM5 for running kernel bypass networking. (DPDK)☆15Updated last year
- A parallel and distributed simulator for thousand-core chips☆22Updated 6 years ago
- ☆51Updated 6 months ago
- ☆18Updated 3 years ago
- ☆36Updated 2 months ago
- Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 …☆19Updated 4 years ago
- A Programmable Hardware Architecture for Network Transport Logic☆34Updated 3 years ago
- ☆30Updated 9 years ago
- ☆45Updated 2 years ago
- FpgaNIC is an FPGA-based Versatile 100Gb SmartNIC for GPUs [ATC 22]☆123Updated last year
- The Artifact of NeoMem: Hardware/Software Co-Design for CXL-Native Memory Tiering☆39Updated 5 months ago
- An FPGA-based NetTLP adapter☆24Updated 4 years ago
- Examples of DPU programs using the UPMEM DPU SDK☆38Updated 3 months ago
- An infrastructure for inline acceleration of network applications☆30Updated 3 years ago
- HW/SW co-designed end-host RPC stack☆19Updated 3 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆41Updated 7 years ago
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆20Updated 6 years ago
- corundum work on vu13p☆18Updated last year
- Gem5 with PCI Express integrated.☆15Updated 6 years ago
- The gem5-X open source framework (based on the gem5 simulator)☆38Updated last year
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- pcie-bench code for NetFPGA/VCU709 cards☆34Updated 6 years ago
- An FPGA-based full-stack in-storage computing system.☆36Updated 4 years ago
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆20Updated 2 years ago