microsoft / DUALinks
DUA, is a communication architecture that provides uniform access for FPGA to data center resources. Without being limited by machine boundaries, DUA provides global names and a common interface for communicating across various resources, the underlying network automatically routing traffic and managing resource multiplexing.
☆40Updated 3 years ago
Alternatives and similar repositories for DUA
Users that are interested in DUA are comparing it to the libraries listed below
Sorting:
- PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing☆104Updated 2 years ago
- ☆71Updated 10 months ago
- ☆35Updated 4 years ago
- Clio, ASPLOS'22.☆78Updated 3 years ago
- ☆78Updated 3 months ago
- An Agile Chisel-Based SoC Design Framework☆26Updated 3 years ago
- ☆20Updated 4 years ago
- ☆34Updated 9 years ago
- P4 compatible HLS modules☆11Updated 7 years ago
- ☆15Updated 2 years ago
- Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators☆97Updated 5 months ago
- AMD OpenNIC driver includes the Linux kernel driver☆69Updated 11 months ago
- ☆168Updated 4 years ago
- FpgaNIC is an FPGA-based Versatile 100Gb SmartNIC for GPUs [ATC 22]☆136Updated 2 years ago
- corundum work on vu13p☆22Updated 2 years ago
- pcie-bench code for NetFPGA/VCU709 cards☆42Updated 7 years ago
- Framework for FPGA-accelerated Middlebox Development☆48Updated 2 years ago
- A parallel and distributed simulator for thousand-core chips☆27Updated 7 years ago
- ☆53Updated 3 years ago
- RoCE v2 hardware and software implementation☆168Updated last year
- ETHZ Heterogeneous Accelerated Compute Cluster.☆38Updated 2 months ago
- A Programmable Hardware Architecture for Network Transport Logic☆35Updated 4 years ago
- RecoNIC is a software/hardware shell used to enable network-attached processing within an RDMA-featured SmartNIC for scale-out computing.☆153Updated 8 months ago
- SmartNIC☆14Updated 6 years ago
- AMD OpenNIC Shell includes the HDL source files☆134Updated 11 months ago
- Distributed Accelerator OS☆63Updated 3 years ago
- ☆53Updated last year
- A Fast, Scalable and Programmable Packet Scheduler in Hardware☆37Updated 6 years ago
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆25Updated 3 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆45Updated 8 years ago