wenxuan-hu / SSRL_work
work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework
☆28Updated 2 years ago
Alternatives and similar repositories for SSRL_work:
Users that are interested in SSRL_work are comparing it to the libraries listed below
- Verification IP for APB protocol☆56Updated 4 years ago
- ☆24Updated 3 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆24Updated 2 years ago
- Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence☆29Updated 4 years ago
- AXI Interconnect☆47Updated 3 years ago
- Verification AXI-4 bus standard using UVM and System Verilog☆15Updated 6 years ago
- Sample UVM code for axi ram dut☆30Updated 3 years ago
- UART design in SV and verification using UVM and SV☆39Updated 5 years ago
- DDR3 function verification environment in UVM☆22Updated 6 years ago
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆17Updated 3 years ago
- Verification IP for APB protocol☆26Updated 4 years ago
- ☆16Updated 2 years ago
- AHB-APB UVM Verification Environment☆17Updated 9 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆16Updated last week
- UVM resource from github, run simulation use YASAsim flow☆26Updated 4 years ago
- Verification IP for SPI protocol☆17Updated 4 years ago
- ☆36Updated last year
- UVM testbench environment consisting of an APB driver, high level SPI controller model, and SPI verification testbench based upon an LPC2…☆8Updated last month
- Maven Silicon Project☆17Updated 6 years ago
- ☆17Updated 3 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆57Updated last year
- This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.☆37Updated 4 years ago
- UVM Testbench for synchronus fifo☆16Updated 4 years ago
- AHB to APB Bridge VIP☆28Updated 5 years ago
- A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…☆14Updated 6 years ago
- a very simple risc_cpu verification demo with uvm☆22Updated 5 years ago
- Master and Slave made using AMBA AXI4 Lite protocol.☆26Updated 4 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆81Updated last year
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆36Updated 2 years ago
- Verification IP for I2C protocol☆41Updated 3 years ago