work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework
☆40Nov 24, 2022Updated 3 years ago
Alternatives and similar repositories for SSRL_work
Users that are interested in SSRL_work are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- DDR3 function verification environment in UVM☆26Apr 1, 2018Updated 8 years ago
- Simple AMBA VIP, Include axi/ahb/apb☆33Jul 4, 2024Updated last year
- ☆49Nov 3, 2023Updated 2 years ago
- This is a open source project from UVM Community and it is based on an Ethernet Switch System-on-Chip (SoC).☆15May 16, 2021Updated 4 years ago
- Verification IP for APB protocol☆77Dec 18, 2020Updated 5 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆80Mar 21, 2024Updated 2 years ago
- General Purpose I/O agent written in UVM☆17Jun 29, 2017Updated 8 years ago
- ☆29May 11, 2021Updated 4 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆128Jul 22, 2021Updated 4 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆14Nov 9, 2015Updated 10 years ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆21Sep 14, 2023Updated 2 years ago
- Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence☆40Jun 24, 2020Updated 5 years ago
- UVM Clock and Reset Agent☆15Jun 29, 2017Updated 8 years ago
- ☆12May 8, 2022Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆111Jul 2, 2023Updated 2 years ago
- A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…☆17Jul 7, 2018Updated 7 years ago
- ☆68Jan 7, 2023Updated 3 years ago
- Sample UVM code for axi ram dut☆39Dec 14, 2021Updated 4 years ago
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆15Jan 4, 2019Updated 7 years ago
- PCIE 5.0 Graduation project (Verification Team)☆105Jan 27, 2024Updated 2 years ago
- SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core☆162Jul 16, 2018Updated 7 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆26Mar 8, 2026Updated 2 months ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆31Jun 1, 2022Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- UVM components for DSP tasks (MODulation/DEModulation)☆16Mar 2, 2022Updated 4 years ago
- ☆19Aug 11, 2022Updated 3 years ago
- uvm AXI BFM(bus functional model)☆268Jun 23, 2013Updated 12 years ago
- Implements a simple UVM based testbench for a simple memory DUT.☆12Oct 26, 2019Updated 6 years ago
- UVM testbench for verifying the Pulpino SoC☆14Mar 23, 2020Updated 6 years ago
- A small DNN library for RISC-V, using RISC-V Vector and Matrix extensions☆11Mar 13, 2025Updated last year
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆36May 3, 2026Updated last week
- A configurable general purpose graphics processing unit for☆12May 18, 2019Updated 6 years ago
- VIP for AXI Protocol☆171May 24, 2022Updated 3 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- UVM Book Examples - A Practical Guide to Adopting the Universal Verification Methodology (UVM) Second Edition☆32Jan 20, 2014Updated 12 years ago
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆64Aug 9, 2020Updated 5 years ago
- SystemVerilog Design Patterns☆26Mar 11, 2015Updated 11 years ago
- An AXI4 crossbar implementation in SystemVerilog☆225May 2, 2026Updated last week
- CORE-V MCU UVM Environment and Test Bench☆26Jul 19, 2024Updated last year
- ☆26May 31, 2021Updated 4 years ago
- UVM Testbench to verify serial transmission of data between SPI master and slave☆54Jul 4, 2020Updated 5 years ago