Alternatives and similar repositories for bitman

Users that are interested in bitman are comparing it to the libraries listed below

• khoapham / efcad
  ☆16Updated 6 years ago
• FPGA-Research / zynq-ultrascale-readback-capture
  This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…
  ☆18Updated 6 years ago
• intel / rapid-design-methods-for-developing-hardware-accelerators
  ☆88Updated 3 years ago
• maltanar / axi-in-chisel
  Examples for creating AXI-interfaced peripherals in Chisel
  ☆76Updated 10 years ago
• FPGA-Research / fos
  FOS - FPGA Operating System
  ☆73Updated 5 years ago
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆75Updated 5 years ago
• unihd-cag / openhmc
  openHMC - an open source Hybrid Memory Cube Controller
  ☆50Updated 9 years ago
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆113Updated 3 years ago
• maltanar / fpga-tidbits
  Chisel components for FPGA projects
  ☆128Updated 2 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago
• intel / aib-phy-hardware
  ☆67Updated 3 years ago
• ucb-bar / sha3
  ☆82Updated last year
• RSPwFPGAs / opae-xilinx
  OPAE porting to Xilinx FPGA devices.
  ☆39Updated 5 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆61Updated 5 years ago
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆53Updated 5 years ago
• UCLA-VAST / RapidStream
  [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
  ☆127Updated 3 years ago
• li3tuo4 / rc-fpga-zcu
  Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
  ☆64Updated 2 years ago
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆43Updated 5 years ago
• hlslibs / matchlib_connections
  Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)
  ☆43Updated this week
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆54Updated 5 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆77Updated 5 months ago
• LBL-CoDEx / OpenSoCFabric
  OpenSoC Fabric - A Network-On-Chip Generator
  ☆175Updated 5 years ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆88Updated 4 years ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 5 years ago
• forconesi / nfmac10g
  Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC
  ☆70Updated 8 years ago
• alexforencich / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆67Updated 4 months ago
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆144Updated last year
• eliaskousk / parallella-riscv
  RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
  ☆105Updated 7 years ago
• mit-ll / CEP
  The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…
  ☆67Updated 3 years ago
• fpgasystems / davos
  Distributed Accelerator OS
  ☆63Updated 3 years ago