kmanev / ZynqUSp-AXI-SpeedtestLinks
☆16Updated 6 years ago
Alternatives and similar repositories for ZynqUSp-AXI-Speedtest
Users that are interested in ZynqUSp-AXI-Speedtest are comparing it to the libraries listed below
Sorting:
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆71Updated 5 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆83Updated 2 years ago
- eyeriss-chisel3☆40Updated 3 years ago
- A systolic array matrix multiplier☆29Updated 6 years ago
- ☆38Updated 6 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆71Updated 2 weeks ago
- Fast and Flexible FPGA development using Hierarchical Partial Reconfiguration (FPT 2022)☆14Updated last year
- ☆71Updated 6 years ago
- HLS for Networks-on-Chip☆37Updated 4 years ago
- ☆45Updated last year
- HLS implemented systolic array structure☆41Updated 8 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.☆176Updated 3 months ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Updated 2 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆109Updated 5 years ago
- ☆38Updated 8 months ago
- AMD University Program HLS tutorial☆120Updated last year
- Hardware accelerator for convolutional neural networks☆60Updated 3 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 5 years ago
- ☆72Updated 2 years ago
- An integrated CGRA design framework☆91Updated 8 months ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆33Updated 4 years ago
- ☆79Updated 11 years ago
- Systolic array implementations for Cholesky, LU, and QR decomposition☆47Updated last year
- NVDLA small config implementation on Zynq ZCU104 (evaluation)☆24Updated 6 years ago
- Train and deploy LUT-based neural networks on FPGAs☆102Updated last year
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆177Updated 5 years ago
- Verilog implementation of Softmax function☆77Updated 3 years ago
- A low power platform based on X-HEEP and integrating the ESL-CGRA☆15Updated 3 weeks ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆97Updated this week
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆157Updated 9 months ago