☆17Nov 29, 2019Updated 6 years ago
Alternatives and similar repositories for ZynqUSp-AXI-Speedtest
Users that are interested in ZynqUSp-AXI-Speedtest are comparing it to the libraries listed below
Sorting:
- ZCU102 two IMX274 camera design.☆12Feb 3, 2023Updated 3 years ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆37Sep 25, 2019Updated 6 years ago
- Fast and Flexible FPGA development using Hierarchical Partial Reconfiguration (FPT 2022)☆15Mar 21, 2024Updated last year
- ☆14Mar 13, 2023Updated 2 years ago
- zynqmp-zcu102 hacks☆20Sep 15, 2017Updated 8 years ago
- ☆17Feb 3, 2023Updated 3 years ago
- ☆16Oct 25, 2022Updated 3 years ago
- NVDLA small config implementation on Zynq ZCU104 (evaluation)☆24Mar 25, 2019Updated 6 years ago
- autonomous driving contest reference kit☆10Dec 2, 2021Updated 4 years ago
- Automatic Verilog/SystemVerilog verification platform generation, support for one-click simulation☆12Aug 8, 2019Updated 6 years ago
- This is the repository containing the implementation of sparse dense matrix multiplication for the matrix dimension of 560 x 560.☆10Jul 7, 2021Updated 4 years ago
- Static Block Floating Point Quantization for CNN☆37Jun 9, 2021Updated 4 years ago
- ☆13Apr 12, 2023Updated 2 years ago
- ☆10Nov 5, 2019Updated 6 years ago
- Github Repo for Embedded FPGA course by Vincent Claes☆12Mar 10, 2023Updated 2 years ago
- ChipScope / ILA using XVC (XIlinx Virtual Cable Over PCIe) with a PR (Partial Reconfiguration) design Example.☆14Jun 1, 2017Updated 8 years ago
- 💤 Relaxation labelling to refine edge detection 💤☆11Jul 29, 2019Updated 6 years ago
- POSIX-compatible tiny multi-threading library for Intel Nios II / Xilinx Zynq-7000☆13Jun 14, 2020Updated 5 years ago
- This repository contains the hardware implementation for Static BFP convolution on FPGA☆10Oct 15, 2019Updated 6 years ago
- eBPF kernels and user space tools for BeagleBone SBCs☆10Jan 16, 2022Updated 4 years ago
- A configuration controller solution allowing a Zynq device to configure downstream FPGAs☆14Oct 5, 2015Updated 10 years ago
- 基于Xilinx FPGA的通用型 CNN卷积神经网络加速器，本设计基于KV260板卡，MpSoC架构均可移植☆18Dec 13, 2024Updated last year
- ☆10Jun 28, 2019Updated 6 years ago
- Express DLA implementation for FPGA, revised based on NVDLA.☆11Oct 17, 2019Updated 6 years ago
- 文档编写☆13Sep 19, 2020Updated 5 years ago
- An LLVM pass to prove that an II works for the given loop for Vitis HLS☆11Aug 22, 2021Updated 4 years ago
- HW/SW co-design of sentence-level energy optimizations for latency-aware multi-task NLP inference☆54Mar 24, 2024Updated last year
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆13May 14, 2019Updated 6 years ago
- OV7670 Camera Module Initialize with XILINX ZYNQ Driver☆11Oct 22, 2016Updated 9 years ago
- ☆15Oct 20, 2025Updated 4 months ago
- Video4Linux example application☆13Nov 13, 2012Updated 13 years ago
- ☆11Mar 16, 2022Updated 3 years ago
- Lower chisel memories to SRAM macros☆13Mar 25, 2024Updated last year
- Updated Xilinx PYNQ for Zynq + ZynqMP python HW acceleration development☆12Mar 16, 2018Updated 7 years ago
- HLS project modeling various sparse accelerators.☆12Jan 11, 2022Updated 4 years ago
- Ultra96 PYNQ入门之一次简单的总结☆14May 21, 2020Updated 5 years ago
- Serverless setup using node.js☆14Jun 8, 2021Updated 4 years ago
- A NVDLA Loadable Parser.☆12Mar 2, 2022Updated 4 years ago
- This repository contains papers for a comprehensive survey on accelerated generation techniques in Large Language Models (LLMs).☆11May 24, 2024Updated last year