uwsampa / mcpat
McPAT modeling framework
☆12Updated 10 years ago
Alternatives and similar repositories for mcpat:
Users that are interested in mcpat are comparing it to the libraries listed below
- ☆25Updated 11 months ago
- MAESTRO binary release☆22Updated 5 years ago
- A reference implementation of the Mind Mappings Framework.☆29Updated 3 years ago
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆20Updated 6 years ago
- MAERI public release☆31Updated 3 years ago
- gem5 repository to study chiplet-based systems☆71Updated 5 years ago
- ☆23Updated 4 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆41Updated 7 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆70Updated 5 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 2 years ago
- ☆25Updated 3 years ago
- ☆33Updated 3 years ago
- Hybrid Memory Cube Simulation & Research Infrastructure☆16Updated last year
- Benchmarks for Accelerator Design and Customized Architectures☆120Updated 5 years ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 2 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆79Updated last year
- Stencil with Optimized Dataflow Architecture Compiler☆16Updated 4 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆18Updated 6 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆71Updated 3 years ago
- agile hardware-software co-design☆47Updated 3 years ago
- Heterogenous ML accelerator☆18Updated 6 months ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆38Updated 6 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- This is a general-purpose simulator for unary computing based on PyTorch, with the paper accepted to ISCA 2020 and awarded IEEE Micro Top…☆42Updated last year
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆35Updated 2 years ago
- ☆35Updated 3 years ago
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆62Updated last year
- ☆71Updated 2 years ago
- EQueue Dialect☆40Updated 3 years ago