snu-comparch / TenderLinks
Tender: Accelerating Large Language Models via Tensor Decompostion and Runtime Requantization (ISCA'24)
☆20Updated last year
Alternatives and similar repositories for Tender
Users that are interested in Tender are comparing it to the libraries listed below
Sorting:
- ☆29Updated this week
- ☆49Updated last month
- ☆108Updated last year
- [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning☆100Updated 11 months ago
- UPMEM LLM Framework allows profiling PyTorch layers and functions and simulate those layers/functions with a given hardware profile.☆34Updated 2 weeks ago
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆51Updated 4 months ago
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆29Updated last year
- ☆78Updated last year
- ☆179Updated last year
- A co-design architecture on sparse attention☆51Updated 4 years ago
- ☆48Updated 4 years ago
- MICRO22 artifact evaluation for Sparseloop☆44Updated 3 years ago
- NeuPIMs: NPU-PIM Heterogeneous Acceleration for Batched LLM Inferencing☆90Updated last year
- ☆51Updated last year
- PIM-DL: Expanding the Applicability of Commodity DRAM-PIMs for Deep Learning via Algorithm-System Co-Optimization☆32Updated last year
- ☆41Updated 2 weeks ago
- Official implementation of EMNLP'23 paper "Revisiting Block-based Quantisation: What is Important for Sub-8-bit LLM Inference?"☆23Updated last year
- Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…☆17Updated 4 months ago
- Implementation of Microscaling data formats in SystemVerilog.☆23Updated last month
- [HPCA 2023] ViTCoD: Vision Transformer Acceleration via Dedicated Algorithm and Accelerator Co-Design☆115Updated 2 years ago
- PALM: A Efficient Performance Simulator for Tiled Accelerators with Large-scale Model Training☆18Updated last year
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆146Updated 6 months ago
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆43Updated last year
- ☆28Updated 2 years ago
- Artifact for paper "PIM is All You Need: A CXL-Enabled GPU-Free System for LLM Inference", ASPLOS 2025☆85Updated 3 months ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆87Updated 3 months ago
- Torch2Chip (MLSys, 2024)☆53Updated 4 months ago
- A bit-level sparsity-awared multiply-accumulate process element.☆16Updated last year
- Artifact material for [HPCA 2025] #2108 "UniNDP: A Unified Compilation and Simulation Tool for Near DRAM Processing Architectures"☆37Updated 8 months ago
- EDA toolchain for processing-in-memory architectures, including an architecture synthesizer, a compiler, and a simulator☆14Updated 2 months ago