IP Cores that can be used within Vivado
☆27May 18, 2021Updated 4 years ago
Alternatives and similar repositories for vivado-ip-cores
Users that are interested in vivado-ip-cores are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog IP Cores & Tests☆13May 3, 2018Updated 7 years ago
- ☆18Sep 16, 2020Updated 5 years ago
- Polar Decoder☆12Jan 19, 2023Updated 3 years ago
- Simple demo showing how to use the ping pong FIFO☆16May 2, 2016Updated 9 years ago
- IP cores for the FPGA Libre project☆12Aug 7, 2017Updated 8 years ago
- NordVPN Threat Protection Pro™ • AdTake your cybersecurity to the next level. Block phishing, malware, trackers, and ads. Lightweight app that works with all browsers.
- A parameterizable Vivado HLS project (C/C++) that implements a master and slave AXI-Stream to AXI-Memory-Mapped data mover (AXI-S default…☆16Aug 29, 2018Updated 7 years ago
- UDP/IP Core☆12Jul 17, 2014Updated 11 years ago
- Four versions of MIPS 32bit implemented in Verilog using Vivado, ready for Simulation and Nexys4 DDR Board☆12Sep 15, 2022Updated 3 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆17Mar 14, 2020Updated 6 years ago
- An open-source VHDL library for FPGA design.☆32Jun 2, 2022Updated 3 years ago
- Picorv32 SoC that uses only BRAM, not flash memory☆13Nov 27, 2018Updated 7 years ago
- Direct Access Memory for MPSoC☆13Feb 28, 2026Updated last month
- Verilog network module. Models network traffic from pcap to AXI-Stream☆24Apr 24, 2021Updated 4 years ago
- VHDL Bypass descriptor controller for Xilinx DMA IP for PCIe☆18Oct 23, 2019Updated 6 years ago
- NordVPN Special Discount Offer • AdSave on top-rated NordVPN 1 or 2-year plans with secure browsing, privacy protection, and support for for all major platforms.
- mirror of https://git.elphel.com/Elphel/x393_sata☆35May 12, 2020Updated 5 years ago
- verilog/FPGA hardware description for very simple GPU☆16Apr 9, 2019Updated 6 years ago
- Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).☆62Jul 5, 2022Updated 3 years ago
- PulseRain FP51 MCU, with peripherals☆17Mar 20, 2018Updated 8 years ago
- FPGA Additive White Gaussian Noise Generator Using the Box Mueller Method☆11Oct 7, 2016Updated 9 years ago
- an sata controller using smallest resource.☆17Feb 5, 2014Updated 12 years ago
- MIDI synthesizer written in VHDL☆13Apr 3, 2012Updated 13 years ago
- MicroPython port to litex FPGA platforms☆41Apr 7, 2020Updated 5 years ago
- Transfer data from DDR memory to AXI4-Stream Data FIFO and back through AXI DMA☆23May 20, 2019Updated 6 years ago
- Wordpress hosting with auto-scaling on Cloudways • AdFully Managed hosting built for WordPress-powered businesses that need reliable, auto-scalable hosting. Cloudways SafeUpdates now available.
- Polar coding, decoding, and testing☆13Oct 11, 2023Updated 2 years ago
- ☆12Jul 20, 2022Updated 3 years ago
- Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.☆32Jun 8, 2017Updated 8 years ago
- Repository containing the DSP gateware cores☆14Mar 9, 2026Updated 2 weeks ago
- OscillatorIMP ecosystem FPGA IP sources☆27Feb 22, 2026Updated last month
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆54Dec 6, 2023Updated 2 years ago
- RTL implementation of a ray-tracing GPU☆15Dec 18, 2012Updated 13 years ago
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- A C++ template library for FPGAs on top of Xilinx Vivado HLS☆14Feb 2, 2017Updated 9 years ago
- Wordpress hosting with auto-scaling on Cloudways • AdFully Managed hosting built for WordPress-powered businesses that need reliable, auto-scalable hosting. Cloudways SafeUpdates now available.
- File editor for the Xilinx AXI Traffic Generator IP☆17Feb 9, 2026Updated last month
- HDL code for the MATRIX Voice's Spartan 6 FPGA http://voice.matrix.one☆23Sep 12, 2023Updated 2 years ago
- Implementation of Wireless communication blocks such as FFT, OFDM receiver, Polar code decoder in a FPGA using Vivado HLS☆30Dec 17, 2020Updated 5 years ago
- A collection of VHDL projects for generating VGA output☆25Nov 26, 2018Updated 7 years ago
- ☆24Apr 18, 2021Updated 4 years ago
- Saleae High-Level Data Link Control (HDLC) Analyzer☆15Jul 2, 2025Updated 8 months ago
- Verilog I2C Slave☆24Aug 11, 2014Updated 11 years ago