IP Cores that can be used within Vivado
☆27May 18, 2021Updated 5 years ago
Alternatives and similar repositories for vivado-ip-cores
Users that are interested in vivado-ip-cores are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog IP Cores & Tests☆13May 3, 2018Updated 8 years ago
- Polar Decoder☆12Jan 19, 2023Updated 3 years ago
- Xilinx IP repository☆13May 5, 2018Updated 8 years ago
- PolarDecoders implemented in Verilog. SC, SCL, CA-SCL and CA-PC-SCL are supported.☆10Sep 24, 2021Updated 5 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆17Mar 14, 2020Updated 6 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- ☆18Sep 16, 2020Updated 6 years ago
- Direct Access Memory for MPSoC☆13Aug 7, 2026Updated 2 months ago
- ☆18Sep 25, 2026Updated 3 weeks ago
- Simple demo showing how to use the ping pong FIFO☆17May 2, 2016Updated 10 years ago
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆12Jan 8, 2022Updated 4 years ago
- Four versions of MIPS 32bit implemented in Verilog using Vivado, ready for Simulation and Nexys4 DDR Board☆13Sep 15, 2022Updated 4 years ago
- IP cores for the FPGA Libre project☆12Aug 7, 2017Updated 9 years ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆37May 12, 2020Updated 6 years ago
- UDP/IP Core☆12Jul 17, 2014Updated 12 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- 异步FIFO的内部实现☆25Aug 26, 2018Updated 8 years ago
- Verilog wishbone components☆135Jan 5, 2024Updated 2 years ago
- A parameterizable Vivado HLS project (C/C++) that implements a master and slave AXI-Stream to AXI-Memory-Mapped data mover (AXI-S default…☆16Aug 29, 2018Updated 8 years ago
- Transfer data from DDR memory to AXI4-Stream Data FIFO and back through AXI DMA☆23May 20, 2019Updated 7 years ago
- Real Digital Vivado IP Library☆10Nov 13, 2022Updated 3 years ago
- Xilinx Virtual Cable server written in python connecting Xilinx with different JTAG adapters☆12Dec 20, 2013Updated 12 years ago
- Picorv32 SoC that uses only BRAM, not flash memory☆13Nov 27, 2018Updated 7 years ago
- pcie-bench code for NetFPGA/VCU709 cards☆46Jul 27, 2018Updated 8 years ago
- ☆47Apr 11, 2017Updated 9 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Verilog network module. Models network traffic from pcap to AXI-Stream☆24Apr 24, 2021Updated 5 years ago
- Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).☆62Jul 5, 2022Updated 4 years ago
- VHDL Bypass descriptor controller for Xilinx DMA IP for PCIe☆19Oct 23, 2019Updated 6 years ago
- verilog/FPGA hardware description for very simple GPU☆17Apr 9, 2019Updated 7 years ago
- PulseRain FP51 MCU, with peripherals☆17Mar 20, 2018Updated 8 years ago
- The official repository of the local FPGA Development Kit.☆22Apr 30, 2019Updated 7 years ago
- IPv4/UDP stack written in VHDL code, for interfacing with an FPGA over Ethernet☆13Jun 2, 2021Updated 5 years ago
- High level Data Link Layer Control (HDLC) Protocol (16 bit) implementation using VHDL hardware description language.☆31Dec 1, 2016Updated 9 years ago
- 正点原子开拓者&新起点FPGA开发板例程☆16Nov 29, 2019Updated 6 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- FPGA Additive White Gaussian Noise Generator Using the Box Mueller Method☆11Oct 7, 2016Updated 10 years ago
- MT29F128G based NAND flash controller☆10Jun 17, 2021Updated 5 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Dec 9, 2020Updated 5 years ago
- Computational Storage Device based on the open source project OpenSSD.☆32Oct 25, 2020Updated 5 years ago
- MIDI synthesizer written in VHDL☆13Apr 3, 2012Updated 14 years ago
- SHA-256 IP core for ZedBoard (Zynq SoC)☆31Jun 22, 2018Updated 8 years ago
- ☆38Updated this week