Alternatives and similar repositories for BrianHG-DDR3-Controller:

Users that are interested in BrianHG-DDR3-Controller are comparing it to the libraries listed below

• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆79Updated 4 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆39Updated last month
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆89Updated 4 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆79Updated 2 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆69Updated 2 years ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆66Updated 2 years ago
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆60Updated 2 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆63Updated 4 years ago
• defparam / PCI2Nano-RTL
  An open source FPGA PCI core & 8250-Compatible PCI UART core
  ☆42Updated 4 years ago
• freecores / uart16550
  UART 16550 core
  ☆33Updated 10 years ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆36Updated 3 years ago
• dmitrodem / p1735_decryptor
  IEEE P1735 decryptor for VHDL
  ☆31Updated 9 years ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆42Updated 4 years ago
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆79Updated 4 years ago
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆65Updated 7 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆60Updated 3 years ago
• ZiyangYE / General-Slow-DDR3-Interface
  A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.
  ☆38Updated 10 months ago
• nand2mario / ddr3-tang-primer-20k
  DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.
  ☆51Updated last year
• fjullien / jtag_vpi
  TCP/IP controlled VPI JTAG Interface.
  ☆65Updated 2 months ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆54Updated 2 years ago
• lekgolo167 / enxor-logic-analyzer
  FPGA Logic Analyzer and GUI
  ☆120Updated 2 years ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆109Updated 6 years ago
• MJoergen / HyperRAM
  Portable HyperRAM controller
  ☆54Updated 3 months ago
• janschiefer / verilog_spi
  A simple Verilog SPI master / slave implementation featuring all 4 modes.
  ☆51Updated 4 years ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆93Updated 4 years ago
• dirjud / Nitro-Parts-lib-SPI
  Verilog SPI master and slave
  ☆51Updated 9 years ago
• esynr3z / usb20dev
  USB 2.0 FS Device controller IP core written in SystemVerilog
  ☆35Updated 6 years ago
• esynr3z / proto245
  🔴 SystemVerilog FPGA cores to communicate with FTDI Synchronous/Asynchronous FIFOs (FT245 protocol)
  ☆39Updated 3 years ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆50Updated 5 years ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆77Updated last week