zhaishaomin / ring_network-based-multicore-Links
多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency
☆26Updated 9 years ago
Alternatives and similar repositories for ring_network-based-multicore-
Users that are interested in ring_network-based-multicore- are comparing it to the libraries listed below
Sorting:
- ☆31Updated 5 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Updated 7 years ago
- YSYX RISC-V Project NJU Study Group☆16Updated 11 months ago
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆38Updated 8 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆84Updated 7 years ago
- Design and UVM-TB of RISC -V Microprocessor☆31Updated last year
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 7 years ago
- SystemVerilog modules and classes commonly used for verification☆52Updated 2 weeks ago
- verification of simple axi-based cache☆18Updated 6 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Updated 4 years ago
- soc integration script and integration smoke script☆24Updated 3 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆41Updated 3 years ago
- General Purpose AXI Direct Memory Access☆61Updated last year
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆36Updated 3 years ago
- RTL code of some arbitration algorithm☆15Updated 6 years ago
- ☆38Updated 6 years ago
- round robin arbiter☆77Updated 11 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆65Updated 4 years ago
- commit rtl and build cosim env☆15Updated last year
- AXI4 BFM in Verilog☆35Updated 9 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- ☆22Updated 6 years ago
- ☆65Updated 3 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆30Updated 10 months ago
- AXI Interconnect☆54Updated 4 years ago
- System Verilog and Emulation. Written all the five channels.☆35Updated 8 years ago
- SoC Based on ARM Cortex-M3☆34Updated 6 months ago
- Synthesizable and Parameterized Cache Controller in Verilog☆45Updated 2 years ago