Alternatives and similar repositories for ring_network-based-multicore-:

Users that are interested in ring_network-based-multicore- are comparing it to the libraries listed below

• pulp-platform / axi_spi_master
  ☆21Updated 5 years ago
• muzafferkal / axi-bfm
  AXI3 Bus Functional Models (Initiator & Target)
  ☆28Updated 2 years ago
• hyf6661669 / verilog_library
  HYF's high quality verilog codes
  ☆12Updated 4 months ago
• ljgibbslf / basic_cache_core
  ☆27Updated 4 years ago
• pulp-platform / axi2apb
  ☆20Updated 5 years ago
• panweitao / riscvv
  an open source uvm verification platform for e200 (riscv)
  ☆27Updated 7 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆49Updated 11 months ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆74Updated 7 years ago
• TYOD-SOC / RISCV-Accelerator
  ☆36Updated 6 years ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 5 years ago
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆42Updated 4 years ago
• nguyenquanicd / AllArbiterRTLCode
  RTL code of some arbitration algorithm
  ☆14Updated 5 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆40Updated last year
• pulp-platform / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆19Updated 2 months ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆51Updated 2 years ago
• jerralph / riscv-vip
  For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
  ☆60Updated 4 years ago
• yvnr4you / AMBA_AXI3
  System Verilog and Emulation. Written all the five channels.
  ☆34Updated 8 years ago
• chad-q / andes-vector-riscv-dv
  Andes Vector Extension support added to riscv-dv
  ☆15Updated 4 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆92Updated 4 years ago
• govindjeevan / Weighted-Round-Robin-Arbiter
  Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components
  ☆18Updated 7 years ago
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆48Updated 3 years ago
• DawnCarol / OpenC910_Modified
  commit rtl and build cosim env
  ☆15Updated last year
• ptracton / AXI_BFM
  AXI4 BFM in Verilog
  ☆32Updated 8 years ago
• rajshadow / 4-way-set-associative-cache-verilog
  Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy
  ☆41Updated 8 years ago
• tej-chavan / Design-and-Verification-of-DDR3-Memory-Controller
  The memory model was leveraged from micron.
  ☆22Updated 7 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆36Updated 9 years ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆65Updated 5 years ago
• OpenXiangShan / XS-Verilog-Library
  ☆41Updated 2 years ago
• hengfengzhang / soc
  soc integration script and integration smoke script
  ☆22Updated 2 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆56Updated last month