zhaishaomin / ring_network-based-multicore-View external linksLinks
多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency
☆26Aug 28, 2016Updated 9 years ago
Alternatives and similar repositories for ring_network-based-multicore-
Users that are interested in ring_network-based-multicore- are comparing it to the libraries listed below
Sorting:
- 位宽和深度可定制的异步FIFO☆13May 29, 2024Updated last year
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Nov 9, 2015Updated 10 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆14Dec 23, 2022Updated 3 years ago
- Simple demo showing how to use the ping pong FIFO☆16May 2, 2016Updated 9 years ago
- Synthesizable and Parameterized Cache Controller in Verilog☆45Jun 13, 2023Updated 2 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆16Jun 24, 2020Updated 5 years ago
- Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy☆41Oct 23, 2016Updated 9 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆32Nov 6, 2018Updated 7 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆20Dec 8, 2012Updated 13 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- Verification IP for SPI protocol☆20Jul 23, 2020Updated 5 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Mar 10, 2018Updated 7 years ago
- EE577b-Course-Project☆19May 6, 2020Updated 5 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆37Oct 25, 2020Updated 5 years ago
- ☆22Feb 22, 2020Updated 5 years ago
- make your verilog DUT test more smart☆22Sep 9, 2016Updated 9 years ago
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- Verilog-Based-NoC-Simulator☆10May 4, 2016Updated 9 years ago
- soc integration script and integration smoke script☆24Sep 12, 2022Updated 3 years ago
- Connecting SystemC with SystemVerilog☆42Mar 25, 2012Updated 13 years ago
- ☆12Nov 11, 2015Updated 10 years ago
- Generic AHB master stub☆12Jul 17, 2014Updated 11 years ago
- Open SoC Debug Hardware Reference Implementation☆16Jul 15, 2019Updated 6 years ago
- 第四届全国大学生嵌入式比赛SoC☆11Apr 1, 2022Updated 3 years ago
- ASIC Design lab. Pipelined, Cached, Multicore MIPS Processor☆10Aug 23, 2017Updated 8 years ago
- RTL implementation of a ray-tracing GPU☆15Dec 18, 2012Updated 13 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- 标准视频时序生成器☆10Feb 9, 2020Updated 6 years ago
- MT29F128G based NAND flash controller☆10Jun 17, 2021Updated 4 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Aug 22, 2021Updated 4 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆55May 10, 2021Updated 4 years ago
- The memory model was leveraged from micron.☆28Mar 24, 2018Updated 7 years ago
- Verification of Ethernet Switch System Verilog☆11Oct 21, 2016Updated 9 years ago
- Direct Access Memory for MPSoC☆13Jan 27, 2026Updated 2 weeks ago
- ☆16May 10, 2019Updated 6 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Jan 22, 2025Updated last year
- ☆16May 13, 2025Updated 9 months ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- Xilinx IP repository☆13May 5, 2018Updated 7 years ago