zhaishaomin / ring_network-based-multicore-
多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency
☆21Updated 8 years ago
Alternatives and similar repositories for ring_network-based-multicore-:
Users that are interested in ring_network-based-multicore- are comparing it to the libraries listed below
- AXI3 Bus Functional Models (Initiator & Target)☆28Updated 2 years ago
- ☆20Updated 5 years ago
- ☆25Updated 4 years ago
- Andes Vector Extension support added to riscv-dv☆14Updated 4 years ago
- ☆18Updated 5 years ago
- ☆36Updated 6 years ago
- verification of simple axi-based cache☆18Updated 5 years ago
- ☆41Updated 6 years ago
- an open source uvm verification platform for e200 (riscv)☆26Updated 6 years ago
- Contains commonly used UVM components (agents, environments and tests).☆27Updated 6 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated last week
- Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy☆40Updated 8 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 6 years ago
- commit rtl and build cosim env☆14Updated last year
- ☆34Updated 9 months ago
- ☆16Updated 5 years ago
- ☆23Updated 5 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆30Updated 2 months ago
- Connecting SystemC with SystemVerilog☆37Updated 12 years ago
- This is the repository for the IEEE version of the book☆57Updated 4 years ago
- [UNRELEASED] FP div/sqrt unit for transprecision☆19Updated 10 months ago
- ☆42Updated 2 years ago
- General Purpose AXI Direct Memory Access☆48Updated 9 months ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11Updated 3 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆36Updated 2 years ago
- ☆9Updated 4 years ago
- SystemVerilog modules and classes commonly used for verification☆45Updated last month
- soc integration script and integration smoke script☆21Updated 2 years ago