Alternatives and similar repositories for mips_16:

Users that are interested in mips_16 are comparing it to the libraries listed below

• freecores / turbo8051
  turbo 8051
  ☆28Updated 7 years ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆27Updated 9 years ago
• freecores / jtag
  JTAG Test Access Port (TAP)
  ☆32Updated 10 years ago
• rbarzic / nanorv32
  A small 32-bit implementation of the RISC-V architecture
  ☆32Updated 4 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆36Updated 9 months ago
• baochuquan / RISCV-MMU
  ☆14Updated 7 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆78Updated 5 years ago
• freecores / wb_dma
  WISHBONE DMA/Bridge IP Core
  ☆18Updated 10 years ago
• freecores / axi_master
  Generic AXI master stub
  ☆19Updated 10 years ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆33Updated 8 years ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆39Updated 4 years ago
• RoaLogic / adv_dbg_if
  Universal Advanced JTAG Debug Interface
  ☆17Updated 9 months ago
• esynr3z / usb20dev
  USB 2.0 FS Device controller IP core written in SystemVerilog
  ☆33Updated 6 years ago
• antmicro / openssd-nvme
  ☆18Updated 3 years ago
• freecores / wdsp
  DSP WishBone Compatible Cores
  ☆13Updated 10 years ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆29Updated 8 years ago
• freecores / xge_mac
  Ethernet 10GE MAC
  ☆45Updated 10 years ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆35Updated 3 years ago
• shalan / QSPI_XIP_CTRL_DMC
  Quad SPI Flash XIP Controller with a direct mapped cache
  ☆11Updated 4 years ago
• efabless / raptor_soc_template
  Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.
  ☆18Updated 5 years ago
• KutuSystems / XilinxIP
  Xilinx IP repository
  ☆13Updated 6 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆29Updated 3 weeks ago
• freecores / usbhostslave
  USB 1.1 Host and Function IP core
  ☆20Updated 10 years ago
• freecores / ddr3_sdram
  DDR3 SDRAM controller
  ☆18Updated 10 years ago
• rbarzic / ml-ahb-gen
  A Verilog AMBA AHB Multilayer interconnect generator
  ☆12Updated 7 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆62Updated 4 years ago
• grantae / mips32r1_core
  A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA.
  ☆18Updated 9 years ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆42Updated 9 years ago
• amichai-bd / riscv-multi-core-lotr
  RISCV core RV32I/E.4 threads in a ring architecture
  ☆31Updated last year