freecores / embedded_risc
Embedded 32-bit RISC uProcessor with SDRAM Controller
☆25Updated 3 years ago
Alternatives and similar repositories for embedded_risc:
Users that are interested in embedded_risc are comparing it to the libraries listed below
- turbo 8051☆28Updated 7 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 4 years ago
- DDR4 Simulation Project in System Verilog☆33Updated 10 years ago
- Another tiny RISC-V implementation☆54Updated 3 years ago
- Ethernet MAC 10/100 Mbps☆79Updated 5 years ago
- JTAG Test Access Port (TAP)☆32Updated 10 years ago
- USB 1.1 Host and Function IP core☆20Updated 10 years ago
- Hamming ECC Encoder and Decoder to protect memories☆29Updated this week
- USB Full Speed PHY☆39Updated 4 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆61Updated 4 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆86Updated 4 years ago
- USB -> AXI Debug Bridge☆35Updated 3 years ago
- Wishbone controlled I2C controllers☆45Updated 2 months ago
- Ethernet MAC 10/100 Mbps☆24Updated 3 years ago
- ☆53Updated 2 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- Wishbone interconnect utilities☆38Updated 8 months ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆72Updated 9 months ago
- Verilog Modules and Python Scripts for Creating IP Core Build Directories☆29Updated last year
- MIPI CSI-2 RX☆30Updated 3 years ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆28Updated last month
- DSP WishBone Compatible Cores☆13Updated 10 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 4 years ago
- Multi-Technology RAM with AHB3Lite interface☆21Updated 8 months ago
- This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…☆77Updated 4 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- AXI-4 RAM Tester Component☆17Updated 4 years ago
- Platform Level Interrupt Controller☆35Updated 8 months ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆27Updated 3 years ago
- WISHBONE Builder☆14Updated 8 years ago