wujun51227 / coffee-hdlLinks
coffeescript based hardware description language
☆14Updated 3 years ago
Alternatives and similar repositories for coffee-hdl
Users that are interested in coffee-hdl are comparing it to the libraries listed below
Sorting:
- Input / Output Physical Memory Protection Unit for RISC-V☆12Updated 2 years ago
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆26Updated 9 years ago
- HLS for Networks-on-Chip☆35Updated 4 years ago
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- ☆19Updated this week
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
- ☆29Updated 5 years ago
- RTL code of some arbitration algorithm☆14Updated 6 years ago
- Original test vector of RISC-V Vector Extension☆14Updated 4 years ago
- A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS☆28Updated last week
- Public release☆57Updated 6 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆19Updated 7 years ago
- Development of a Network on Chip Simulation using SystemC.☆34Updated 8 years ago
- EE577b-Course-Project☆17Updated 5 years ago
- Contains commonly used UVM components (agents, environments and tests).☆30Updated 7 years ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆15Updated 5 months ago
- Connecting SystemC with SystemVerilog☆41Updated 13 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- 自建 chisel 工程模板☆14Updated 2 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆14Updated 3 years ago
- Pure digital components of a UCIe controller☆67Updated last month
- SystemVerilog modules and classes commonly used for verification☆50Updated 7 months ago
- ☆15Updated 3 months ago
- ☆31Updated 5 months ago
- ☆36Updated 6 years ago
- Design and UVM-TB of RISC -V Microprocessor☆25Updated last year
- ☆10Updated 3 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆63Updated 4 years ago
- Quad cluster of RISC-V cores with peripherals and local memory☆24Updated 3 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year