Alternatives and similar repositories for cagt:

Users that are interested in cagt are comparing it to the libraries listed below

• seabeam / yuu_clock
  UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available
  ☆10Updated 4 years ago
• chad-q / andes-vector-riscv-dv
  Andes Vector Extension support added to riscv-dv
  ☆14Updated 4 years ago
• JoseIuri / UVM_Python_UVMC
  This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…
  ☆15Updated 5 years ago
• imokanj / clk_rst_agent
  UVM Clock and Reset Agent
  ☆13Updated 7 years ago
• isuckatdrifting / Gaia
  Generate UVM testbench framework template files with Python 3
  ☆25Updated 5 years ago
• GuiZhaoCodeSource / Func_Verif_MMU_Code_Source
  Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache
  ☆12Updated 9 years ago
• taichi-ishitani / tue
  Useful UVM extensions
  ☆21Updated 7 months ago
• openhwgroup / core-v-mcu-uvm
  CORE-V MCU UVM Environment and Test Bench
  ☆18Updated 7 months ago
• antoinemadec / uvm_code_gen
  Simple template-based UVM code generator
  ☆23Updated 2 years ago
• svunit / svmock
  A mock framework for use with SVUnit
  ☆15Updated last year
• taichi-ishitani / tvip-common
  ☆12Updated 8 months ago
• seabeam / yuu_vip_gen
  UVM VIP architecture generator
  ☆19Updated 4 years ago
• Mochenx / sv_csv_parser
  A CSV file parser, written in SystemVerilog
  ☆25Updated 8 years ago
• jiacaiyuan / uvm-generator
  UVM Auto Generate ; Verify Project Build; Verilog Instance
  ☆34Updated 4 years ago
• avashist003 / FIFO_SystemVerilog_Assertion
  Synchronous FIFO design & verification using systemVerilog Assertions
  ☆15Updated 3 years ago
• thinkoco / systemverilog-python
  Systemverilog DPI-C call Python function
  ☆22Updated 3 years ago
• PacoReinaCampo / MPSoC-DV
  Multi-Processor System on Chip verified with UVM/OSVVM/FV
  ☆28Updated last week
• amiq-consulting / yamm
  YAMM package repository
  ☆26Updated last year
• rggen / rggen-sv-rtl
  Common SystemVerilog RTL modules for RgGen
  ☆12Updated 2 weeks ago
• briandong / regModel
  This script builds the UVM register model, based on pre-defined address map in markdown (mk) style
  ☆12Updated 6 years ago
• zhajio1988 / ExtremeDV_UVM
  UVM resource from github, run simulation use YASAsim flow
  ☆27Updated 4 years ago
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆30Updated 2 months ago
• ShonTaware / LowPower
  Various low power labs using sky130
  ☆11Updated 3 years ago
• amiq-consulting / amiq_blog
  Code snippets from articles published on www.amiq.com/consulting/blog
  ☆35Updated 8 months ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 5 years ago
• shady831213 / jarvisuk
  Just A Really Very Impressive Systemverilog UVM Kit
  ☆15Updated 4 years ago
• cclienti / svmodule
  SystemVerilog & Verilog Module I/O parser and printer
  ☆25Updated 3 years ago
• RoaLogic / ahb3lite_pkg
  Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
  ☆17Updated 10 months ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆37Updated 2 years ago
• jg-fossh / uvm-python-verification-lib
  UVM Python Verification Agents Library
  ☆14Updated 3 years ago