Alternatives and similar repositories for pci

Users that are interested in pci are comparing it to the libraries listed below

• freecores / simple_spi
  SPI core
  ☆12Updated 11 years ago
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆81Updated last year
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆89Updated 2 years ago
• CoreyChen922 / sata_2_host_controller
  Sata 2 Host Controller for FPGA implementation
  ☆18Updated 7 years ago
• freecores / uart16550
  UART 16550 core
  ☆37Updated 11 years ago
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆82Updated 5 years ago
• freecores / wb_dma
  WISHBONE DMA/Bridge IP Core
  ☆18Updated 11 years ago
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆64Updated 2 years ago
• zebmehring / Processor-Cache
  A Verilog implementation of a processor cache.
  ☆28Updated 7 years ago
• teekamkhandelwal / asynchronous_fifo
  Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.
  ☆38Updated 4 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 8 months ago
• freecores / ddr3_sdram
  DDR3 SDRAM controller
  ☆18Updated 11 years ago
• Elphel / eddr3
  mirror of https://git.elphel.com/Elphel/eddr3
  ☆41Updated 7 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆79Updated 3 years ago
• Wissance / QuickSPI
  Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
  ☆21Updated 7 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆63Updated 4 years ago
• freecores / axi_master
  Generic AXI master stub
  ☆19Updated 11 years ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆74Updated 2 years ago
• freecores / jtag
  JTAG Test Access Port (TAP)
  ☆36Updated 11 years ago
• defparam / PCI2Nano-RTL
  An open source FPGA PCI core & 8250-Compatible PCI UART core
  ☆43Updated 4 years ago
• kooltzh / xilinx-coe-generator
  Python script for generating Xilinx .coe files for RAM initializing
  ☆17Updated 6 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆50Updated last year
• freecores / reed_solomon_decoder
  Reed Solomon Decoder (204,188)
  ☆12Updated 11 years ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆30Updated last month
• AdriaanSwan / Verilog-I2C-Slave
  Verilog I2C Slave
  ☆24Updated 11 years ago
• geraked / verilog-rle
  Verilog Implementation of Run Length Encoding for RGB Image Compression
  ☆27Updated 4 years ago
• kkudrolli / USB-Host
  Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …
  ☆15Updated 10 years ago
• freecores / mac_layer_switch
  100 MB/s Ethernet MAC Layer Switch
  ☆15Updated 11 years ago
• shalan / MS_QSPI_XIP_CACHE
  AHB-Lite Quad I/O SPI Flash memory controller with direct mapped cache and support for XiP
  ☆14Updated last year
• nelsoncsc / sv_image
  Reusable image processing modules in SystemVerilog
  ☆34Updated 8 years ago