Alternatives and similar repositories for riscv-soc-cores:

Users that are interested in riscv-soc-cores are comparing it to the libraries listed below

• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆38Updated last week
• fjullien / jtag_vpi
  TCP/IP controlled VPI JTAG Interface.
  ☆63Updated last month
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆79Updated 2 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆113Updated last year
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆49Updated 5 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆46Updated last year
• munetomo-maruyama / mmRISC-1
  RISC-V RV32IMAFC Core for MCU
  ☆36Updated 2 weeks ago
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆58Updated 2 years ago
• freecores / jtag
  JTAG Test Access Port (TAP)
  ☆32Updated 10 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆64Updated 2 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆61Updated 4 years ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆39Updated 4 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆29Updated 2 weeks ago
• verilator / example-systemverilog
  ☆35Updated last year
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆52Updated 3 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆60Updated 3 years ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆36Updated 3 years ago
• pulp-platform / axi_spi_slave
  ☆24Updated 3 years ago
• freecores / uart16550
  UART 16550 core
  ☆33Updated 10 years ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆22Updated last year
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆86Updated 4 months ago
• tomverbeure / math
  SpinalHDL Hardware Math Library
  ☆83Updated 7 months ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆57Updated last year
• taichi-ishitani / rggen
  This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
  ☆16Updated 5 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆62Updated this week
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆79Updated 4 years ago
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆74Updated 10 months ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆26Updated last year
• sunyata000 / PODES-M0O
  A VerilogHDL MCU Core based ARMv6 Cortex-M0
  ☆21Updated 5 years ago