JoseIuri / axi4lite2uartLinks
This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.
☆20Updated 6 years ago
Alternatives and similar repositories for axi4lite2uart
Users that are interested in axi4lite2uart are comparing it to the libraries listed below
Sorting:
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆36Updated 3 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆16Updated 10 years ago
- ☆36Updated 9 years ago
- AXI Interconnect☆49Updated 3 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆54Updated 3 years ago
- ☆25Updated 4 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆43Updated last year
- Final Project for my course in Advanced Verification with SystemVerilog OOP☆21Updated 3 years ago
- 100 MB/s Ethernet MAC Layer Switch☆15Updated 10 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- SystemVerilog testbench for an Ethernet 10GE MAC core☆45Updated 9 years ago
- UART -> AXI Bridge☆61Updated 3 years ago
- A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…☆15Updated 6 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆22Updated 6 years ago
- Generic AXI to AHB bridge☆17Updated 10 years ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆32Updated 5 years ago
- Implementation of the PCIe physical layer☆40Updated 3 weeks ago
- PCIE 5.0 Graduation project (Verification Team)☆72Updated last year
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- AHB DMA 32 / 64 bits☆55Updated 10 years ago
- Build an open source, extremely simple DMA.☆22Updated 6 years ago
- Verification AXI-4 bus standard using UVM and System Verilog☆15Updated 7 years ago
- It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.☆17Updated 5 years ago
- ☆20Updated 2 years ago
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆15Updated 2 years ago
- ☆22Updated 4 years ago
- AHB Bus lite v3.0☆15Updated 5 years ago
- asynchronous FIFO that support Non-symmetric aspect ratios(different read and write data widths), First-Word Fall-Through and data counte…☆18Updated last year
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆24Updated 5 years ago
- Must-have verilog systemverilog modules☆36Updated 3 years ago