Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the bus.
☆15Jan 13, 2015Updated 11 years ago
Alternatives and similar repositories for USB-Host
Users that are interested in USB-Host are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- USB2.0 Device Controller IP Core☆15Aug 18, 2023Updated 2 years ago
- USB 2.0 Device IP core using Migen with out-of-box AXI Slave Interface☆13Oct 24, 2017Updated 8 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆30Jun 1, 2022Updated 3 years ago
- USB2.0 Verilog☆20Apr 21, 2019Updated 6 years ago
- Generic AXI to AHB bridge☆18Jul 17, 2014Updated 11 years ago
- Language for simplifying parameterized RTL design☆13Nov 6, 2024Updated last year
- A full-speed device-side USB peripheral core written in Verilog.☆237Oct 30, 2022Updated 3 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆98Jun 6, 2020Updated 5 years ago
- Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.☆13Sep 22, 2025Updated 6 months ago
- USB -> AXI Debug Bridge☆43Jun 5, 2021Updated 4 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆14Mar 26, 2024Updated last year
- Generic AXI master stub☆19Jul 17, 2014Updated 11 years ago
- IPXACT Register Map Generator☆11May 9, 2021Updated 4 years ago
- Design and verify the AMBA AXI protocol with single master-slave from scratch in System Verilog. Debugging the design using both a System…☆12Oct 8, 2017Updated 8 years ago
- SpinalHDL USB system for the ULPI based Arrow DECA board☆20Jan 9, 2022Updated 4 years ago
- Built a test environment using SystemVerilog to verify FIFO. Used QuestaSim to design and verify the module in SystemVerilog and Verilog.…☆36Feb 6, 2019Updated 7 years ago
- tool for converting vcd(value change dump) to ate pattern.☆11Oct 22, 2015Updated 10 years ago
- USB1.1 Host Controller + PHY☆15Aug 4, 2021Updated 4 years ago
- AXI总线连接器☆105Mar 26, 2020Updated 5 years ago
- AXI4 and AXI4-Lite interface definitions☆102Sep 20, 2020Updated 5 years ago
- VIP for AXI Protocol☆165May 24, 2022Updated 3 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆30Dec 26, 2022Updated 3 years ago
- Train a neural network to produce latex source code which generates a given pdf file☆13May 3, 2017Updated 8 years ago
- Computer Architecture UIUC SP 2018☆14May 4, 2018Updated 7 years ago
- Verilog FPGA code : including experimental DSP audio processor☆13Dec 1, 2020Updated 5 years ago
- A RISC-V processor in system verilog☆12Jul 9, 2020Updated 5 years ago
- a fast multiplier implement using verilog☆13Dec 23, 2014Updated 11 years ago
- Design and UVM Verification of an ALU☆11Jun 14, 2024Updated last year
- System Verilog using Functional Verification☆12Apr 8, 2024Updated last year
- ☆10Oct 16, 2023Updated 2 years ago
- AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emula…☆17Mar 22, 2017Updated 9 years ago
- Super Audio CD ISO-Image decoder addon☆16Feb 27, 2026Updated 3 weeks ago
- USB Full-Speed/Hi-Speed Device Controller core for FPGA☆34Nov 23, 2020Updated 5 years ago
- 基于多智能体LLM的中文金融交易框架 - TradingAgents中文增强版☆35Mar 11, 2026Updated last week
- ☆29Jan 6, 2015Updated 11 years ago
- Packaging system for Mac OS X 10.5 and above; heavy optimisations, no redundant packages and a bonus beer theme☆15Apr 25, 2016Updated 9 years ago
- ☆48Jul 2, 2023Updated 2 years ago
- A simple implementation of the Karatsuba multiplication algorithm☆12Apr 2, 2025Updated 11 months ago
- Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language☆17Feb 20, 2019Updated 7 years ago