Alternatives and similar repositories for USB-Host:

Users that are interested in USB-Host are comparing it to the libraries listed below

• wanderingnail / AXI_DMA
  ☆19Updated 2 years ago
• RoaLogic / ahb3lite_apb_bridge
  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
  ☆42Updated 11 months ago
• teekamkhandelwal / asynchronous_fifo
  Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.
  ☆32Updated 4 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆60Updated 3 years ago
• JonathanJing / Asynchronous-FIFO
  Asynchronous fifo in verilog
  ☆33Updated 9 years ago
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆38Updated 2 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆47Updated 3 years ago
• Artityagi123456789 / -100dasofSystemVerilog
  System Verilog using Functional Verification
  ☆10Updated last year
• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆62Updated 4 years ago
• pulp-platform / axi_spi_master
  ☆21Updated 5 years ago
• kumarrishav14 / AMBA_APB
  To design test bench of the APB protocol
  ☆17Updated 4 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆49Updated 11 months ago
• Shehab-Naga / ddr5_phy
  DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
  ☆53Updated last year
• freecores / robust_axi2ahb
  Generic AXI to AHB bridge
  ☆16Updated 10 years ago
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆43Updated 5 years ago
• Ghonimo / Pre_Silicon-AHB-to_APB-Verification
  Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀
  ☆25Updated last year
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆36Updated 9 years ago
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆30Updated last week
• mayurkubavat / SystemVerilog
  SystemVerilog examples and projects
  ☆17Updated 6 years ago
• yvnr4you / AMBA_AXI3
  System Verilog and Emulation. Written all the five channels.
  ☆33Updated 8 years ago
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆58Updated 2 years ago
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆23Updated last year
• techvinodreddy / UART-IP-CORE16550A-Verification-UVM
  The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …
  ☆17Updated 3 years ago
• dadongshangu / async_FIFO
  This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…
  ☆58Updated last year
• red435 / verilog_APB_SPI_interface
  SPI interface connect to APB BUS with Verilog HDL
  ☆29Updated 3 years ago
• kkenshin1 / AXI-Ethernet-UVM
  A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM
  ☆24Updated 2 years ago
• Buddhimah / System-Bus-Design-Verilog
  This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification
  ☆32Updated 5 years ago
• mbits-mirafra / axi4_avip
  ☆28Updated last year
• shubhi704 / APB-Protocol
  ☆43Updated 3 years ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆52Updated 10 months ago