freecores / dvb_s2_ldpc_decoder

Related projects ⓘ

Alternatives and complementary repositories for dvb_s2_ldpc_decoder

• strath-sdr / rfsoc_ofdm
  PYNQ example of an OFDM Transmitter and Receiver on RFSoC.
  ☆44Updated last year
• jfoshea / Viterbi-Decoder-in-Verilog
  An efficient implementation of the Viterbi decoding algorithm in Verilog
  ☆43Updated 7 months ago
• biren15 / Design-and-Verification-of-LDPC-Decoder
  - Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and …
  ☆44Updated 7 years ago
• Lcrypto / FEC-Archive-Verilog
  Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…
  ☆53Updated last year
• dshekhalev / FEC
  FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)
  ☆85Updated 4 months ago
• Teddy-van-Jerry / sdr-psk-fpga
  Dual-Mode PSK Transceiver on SDR With FPGA
  ☆20Updated last month
• lisliyongming / JESD204B
  通过调试ADRV9009和AD9371对jesd204b知识点作进一步学习和总结
  ☆22Updated 5 years ago
• Mshivam2409 / LDPC-Decoder
  Implementation of Partially Parellel LDPC Code Decoder in Verilog
  ☆12Updated 4 years ago
• strath-sdr / rfsoc_notebooks
  A collection of RFSoC introductory notebooks for PYNQ.
  ☆19Updated 3 years ago
• phthinh / OFDM_802_11
  IEEE 802.11 OFDM-based transceiver system
  ☆30Updated 6 years ago
• yugithub / OFDM-baseband
  Verilog实现OFDM基带
  ☆39Updated 8 years ago
• liuguangxi / wifi_ldpc_codec
  Wi-Fi LDPC codec Verilog IP core
  ☆15Updated 5 years ago
• Grootzz / AD9361_TX_MSK
  A project demonstrate how to config ad9361 to TX mode and how to transmit MSK
  ☆52Updated 5 years ago
• liuguangxi / gng
  Gaussian noise generator Verilog IP core
  ☆28Updated last year
• strath-sdr / pynq_agc
  Demonstration of Automatic Gain Control with PYNQ
  ☆11Updated 2 years ago
• Xilinx / RFSoC2x2-PYNQ
  RFSoC2x2 board repo for PYNQ
  ☆17Updated 2 years ago
• Spartak0s / Polar-Codes-Hardware-VHDL
  Polar Codes Implementation on Vhdl
  ☆12Updated 8 years ago
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆99Updated 9 months ago
• catkira / complex_multiplier
  HDL code for a complex multiplier with AXI stream Interface
  ☆13Updated last year
• strath-sdr / rfsoc_qpsk
  PYNQ example of using the RFSoC as a QPSK transceiver.
  ☆90Updated last year
• ghaziiii / Digital-predistortion
  This project aims to implement a digital predistortion algorithm for power amplifier linearizion using vhdl. It contains VHDL design for …
  ☆16Updated last year
• cea-wind / hls_ldpc_dec
  Full piplined LDPC decoder (IEEE 802.16e) implement in FPGA using Xilinx HLS(C synthesis to Verilog Codes)..
  ☆36Updated 5 years ago
• phthinh / OFDM_802_16
  IEEE 802.16 OFDM-based transceiver system
  ☆20Updated 5 years ago
• freecores / ha1588
  Hardware Assisted IEEE 1588 IP Core
  ☆23Updated 10 years ago
• CodePurble / ldpc-fpga
  Playground for implementing LDPC codes on FPGA
  ☆15Updated last year
• coralhu123 / KC705-AD9371
  The implementation of AD9371 on KC705
  ☆20Updated 4 years ago
• Hyacinth2333 / QC_LDPC-ECC
  NMS_decode
  ☆11Updated 4 years ago
• Grootzz / AD9361_TX_GMSK
  A project demonstrate how to config ad9361 to TX mode and how to transmit GMSK
  ☆14Updated 5 years ago
• analogdevicesinc / HighSpeedConverterToolbox
  MATLAB toolbox for ADI high speed converter products
  ☆18Updated 2 weeks ago
• coole198669 / viterbi_decoder
  Hardware Viterbi Decoder in verilog
  ☆22Updated 5 years ago