railnova / zynq-bit2bin
Convert Xilinx FPGA bitstream from the .bit format (as generated by Vivado) into the .bin format (as expected by Linux fpga_manager)
☆10Updated last year
Alternatives and similar repositories for zynq-bit2bin:
Users that are interested in zynq-bit2bin are comparing it to the libraries listed below
- ABC: System for Sequential Logic Synthesis and Formal Verification☆27Updated 2 weeks ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆26Updated 4 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- PicoRV☆44Updated 5 years ago
- ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.☆32Updated this week
- Ethernet MAC 10/100 Mbps☆26Updated 3 years ago
- Library to convert a FASM file into BELs importable into Vivado.☆13Updated last year
- IEEE 754 single precision floating point library in systemverilog and vhdl☆29Updated 4 months ago
- ☆13Updated last month
- S3GA: a simple scalable serial FPGA☆10Updated 2 years ago
- ☆36Updated 7 months ago
- A wishbone controlled PWM (audio) controller☆16Updated last year
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Updated 5 years ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆54Updated this week
- Wishbone to AXI bridge (VHDL)☆41Updated 5 years ago
- A collection of SPI related cores☆17Updated 5 months ago
- An Open Source Link Protocol and Controller☆25Updated 3 years ago
- Chisel Cheatsheet☆33Updated 2 years ago
- Dual-issue RV64IM processor for fun & learning☆60Updated last year
- Another tiny RISC-V implementation☆55Updated 3 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- SoftCPU/SoC engine-V☆54Updated last month
- USB -> AXI Debug Bridge☆36Updated 3 years ago
- Wishbone interconnect utilities☆39Updated 2 months ago
- A reimplementation of a tiny stack CPU☆82Updated last year
- Basic USB 1.1 Host Controller for small FPGAs☆89Updated 4 years ago
- Reusable Verilog 2005 components for FPGA designs☆42Updated 2 months ago
- Open FPGA Modules☆23Updated 6 months ago
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year