Alternatives and similar repositories for HalideAutoGPU:

Users that are interested in HalideAutoGPU are comparing it to the libraries listed below

• ravi-teja-mullapudi / Halide-NN
  CNNs in Halide
  ☆23Updated 9 years ago
• 4vtomat / HTM
  a Halide language To MLIR compiler.
  ☆26Updated 3 years ago
• kumasento / polsca
  Polyhedral High-Level Synthesis in MLIR
  ☆30Updated 2 years ago
• UCLA-VAST / heterohalide
  HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration
  ☆15Updated 4 years ago
• Fibertree-Project / fibertree
  Fibertree emulator
  ☆12Updated 4 months ago
• PolyArch / stream-dataflow
  Public Release of Stream-Dataflow
  ☆14Updated 5 years ago
• cornell-zhang / hcl-dialect
  HeteroCL-MLIR dialect for accelerator design
  ☆41Updated 6 months ago
• harvard-edge / Gables
  ☆14Updated 4 years ago
• GPUPeople / GPUMemManSurvey
  Evaluating different memory managers for dynamic GPU memory
  ☆25Updated 4 years ago
• jerryz123 / onnx-halide
  A Halide backend for ONNX
  ☆10Updated 5 years ago
• dillonhuff / clockwork
  A polyhedral compiler for hardware accelerators
  ☆56Updated 8 months ago
• SwarmArch / T4
  Code released to accompany the ISCA paper: "T4: Compiling Sequential Code for Effective Speculative Parallelization in Hardware"
  ☆28Updated 3 years ago
• heterosys / mlir-vitis
  📥 🎯 (1,4/4) an MLIR-based toolchain with Vitis HLS LLVM input/output targeting FPGAs.
  ☆13Updated 2 years ago
• uwplse / rake
  compiling DSLs to high-level hardware instructions
  ☆22Updated 2 years ago
• spcl / SMI
  Streaming Message Interface: High-Performance Distributed Memory Programming on Reconfigurable Hardware
  ☆16Updated 3 years ago
• microideax / T-DLA
  ☆19Updated 5 years ago
• Blaok / tapa
  TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…
  ☆19Updated 7 months ago
• lesc-ufv / cgra-routing
  SForum 2020 : "A Run-time Hardware Routing Implementation for CGRA Overlays" code and data.
  ☆11Updated 4 years ago
• SamuelBayliss / Potholes
  Polyhedral Compilation tool for High Level Synthesis.
  ☆10Updated 10 years ago
• hipacc / hipacc
  A domain-specific language and compiler for image processing
  ☆76Updated 4 years ago
• ProjectPhysX / PTXprofiler
  A simple profiler to count Nvidia PTX assembly instructions of OpenCL/SYCL/CUDA kernels for roofline model analysis.
  ☆50Updated last week
• NVlabs / iccad2020-GPUgatesim
  ☆13Updated 4 years ago
• StanfordAHA / Halide-to-Hardware_archive
  ☆81Updated last month
• CMU-SAFARI / SPARTA
  A novel spatial accelerator for horizontal diffusion weather stencil computation, as described in ICS 2023 paper by Singh et al. (https:/…
  ☆18Updated last year
• Junyi-Liu / benchmarks-HLS
  Benchmarks, testbenches, and transformed codes for high-level synthesis research
  ☆13Updated 7 years ago
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆21Updated this week
• he-actlab / polymath
  ☆21Updated last month
• sfu-arch / muir
  ☆24Updated 4 years ago
• stganser / polyite
  Polyite: Iterative Schedule Optimization for Parallelization in the Polyhedron Model
  ☆12Updated 5 years ago
• jingpu / Halide-HLS
  HLS branch of Halide
  ☆77Updated 6 years ago