hipacc / hipacc-fpga
Fork of Hipacc generating code for Vivado HLS and Altera OpenCL
☆24Updated 6 years ago
Alternatives and similar repositories for hipacc-fpga:
Users that are interested in hipacc-fpga are comparing it to the libraries listed below
- Rodinia Benchmark Suite for OpenCL-based FPGAs☆31Updated last year
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Updated 5 years ago
- HLS branch of Halide☆77Updated 6 years ago
- Documentation for the entire CGRAFlow☆19Updated 3 years ago
- ☆16Updated 6 years ago
- ☆81Updated last month
- ☆27Updated 5 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- Spector: An OpenCL FPGA Benchmark Suite☆45Updated 6 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- ☆85Updated 2 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- ☆86Updated last year
- DASS HLS Compiler☆29Updated last year
- ☆57Updated last year
- A high-level performance analysis tool for FPGA-based accelerators☆19Updated 7 years ago
- A polyhedral compiler for hardware accelerators☆56Updated 8 months ago
- Project repo for the POSH on-chip network generator☆44Updated last week
- MAERI public release☆31Updated 3 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆21Updated last week
- Repository for the tools and non-commercial data used for the "Accelerator wall" paper.☆49Updated 6 years ago
- Hand-written HDL code and C-based HLS designs for K-means clustering implementations on FPGAs☆48Updated 7 years ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Updated 7 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆49Updated 7 years ago
- ☆29Updated 7 years ago
- MAESTRO binary release☆22Updated 5 years ago
- ☆15Updated 2 years ago