A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs, with error detection capabilities.
☆14Aug 28, 2025Updated 6 months ago
Alternatives and similar repositories for LABFT
Users that are interested in LABFT are comparing it to the libraries listed below
Sorting:
- Repository for compilation and cycle-accurate simulator for scale-out systolic arrays☆16Jan 4, 2023Updated 3 years ago
- Chisel3 implementation of IEEE-754 compliant floating point data type (logic & representation)☆11Dec 16, 2019Updated 6 years ago
- Revisit Kernel Pruning with Lottery Regulated Grouped Convolutions. ICLR 2022☆11Nov 24, 2022Updated 3 years ago
- 6-stage dual-issue in-order superscalar risc-v cpu with floating point unit☆14Updated this week
- A 2D mesh Network on Chip with 5-stage pipelined router, all implemented in Verilog and run on Artix-7 FPGA.☆17May 30, 2023Updated 2 years ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.☆32Aug 28, 2025Updated 6 months ago
- High Granularity Quantizarion for Ultra-Fast Machine Learning Applications on FPGAs☆39Updated this week
- ☆12Nov 24, 2023Updated 2 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆78Updated this week
- ☆59Nov 29, 2025Updated 3 months ago
- awesome image and video denoising, state of the art networks☆10Aug 2, 2019Updated 6 years ago
- Fault Injection Automatic Test Equipment☆16Nov 22, 2021Updated 4 years ago
- Gowin DDR3 Controller with AXI4 Implementation | 高云DDR3内存控制器AXI4接口实现☆28Mar 3, 2024Updated 2 years ago
- ☆11Sep 22, 2022Updated 3 years ago
- RTL code for the DPU chip designed for irregular graphs☆13May 30, 2022Updated 3 years ago
- [FPGA-2022] N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores☆11Dec 16, 2021Updated 4 years ago
- LVGL DEMOS STM32☆10Nov 15, 2022Updated 3 years ago
- Implementation of weight stationary systolic array which has a size of 4x4(scalable) to 256X256☆29Feb 21, 2024Updated 2 years ago
- ☆20Nov 27, 2023Updated 2 years ago
- Sparse CNN Accelerator targeting Intel FPGA☆12Aug 26, 2021Updated 4 years ago
- Models and training scripts for "LSTMs for Keyword Spotting with ReRAM-based Compute-In-Memory Architectures" (ISCAS 2021).☆17Mar 25, 2021Updated 4 years ago
- CPU implementation of the Image stitching using FAST. For FPGA implementation visit tharaka27-SocStitcher.☆12Jun 19, 2020Updated 5 years ago
- Learning Environment-aware and hardware-compatible beam-forming codebooks☆15Mar 8, 2020Updated 6 years ago
- ☆13Apr 15, 2025Updated 11 months ago
- Open-source of MSD framework☆16Sep 12, 2023Updated 2 years ago
- An automated HDC platform☆11Mar 6, 2026Updated last week
- Cryptography accelerator ASIC (for AES128/AES256 and SHA256) using Skywater 130nm process node (main project repo). Taped out in December…☆23Jan 13, 2021Updated 5 years ago
- Extend scipy.integrate with various methods for solve_ivp☆25May 10, 2025Updated 10 months ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Aug 14, 2024Updated last year
- including compiler to encode DGL GNN model to instructions, runtime software to transfer data and control the accelerator, and hardware v…☆14Nov 19, 2023Updated 2 years ago
- Implementation of YOLOv3-tiny + Depthwise Separable Convolution on FPGA☆33Mar 2, 2022Updated 4 years ago
- RDMA programming examples using Soft-RoCE☆13Aug 13, 2021Updated 4 years ago
- [TMLR 2024] Revisiting Random Weight Perturbation for Efficiently Improving Generalization☆12Oct 18, 2024Updated last year
- Implementation of a Systolic Array based sorting engine on an FPGA using Verilog☆11May 11, 2017Updated 8 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆86Nov 26, 2025Updated 3 months ago
- TCP tunnel powered by epoll☆15Dec 16, 2021Updated 4 years ago
- ☆12Mar 11, 2024Updated 2 years ago
- HDL components to build a customized Wishbone crossbar switch☆14May 30, 2019Updated 6 years ago
- ☆40Jun 3, 2023Updated 2 years ago