A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs, with error detection capabilities.
☆14Aug 28, 2025Updated 10 months ago
Alternatives and similar repositories for LABFT
Users that are interested in LABFT are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Repository for compilation and cycle-accurate simulator for scale-out systolic arrays☆16Jan 4, 2023Updated 3 years ago
- Revisit Kernel Pruning with Lottery Regulated Grouped Convolutions. ICLR 2022☆11Nov 24, 2022Updated 3 years ago
- Chisel3 implementation of IEEE-754 compliant floating point data type (logic & representation)☆11Dec 16, 2019Updated 6 years ago
- 6-stage dual-issue in-order superscalar risc-v cpu☆14May 2, 2026Updated last month
- A 2D mesh Network on Chip with 5-stage pipelined router, all implemented in Verilog and run on Artix-7 FPGA.☆21May 30, 2023Updated 3 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.☆37Aug 28, 2025Updated 10 months ago
- Legacy High Granularity Quantizarion 1 - Please use HGQ2 instead (https://github.com/calad0i/HGQ)☆40Mar 13, 2026Updated 3 months ago
- ☆12Nov 24, 2023Updated 2 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆87Apr 26, 2026Updated 2 months ago
- ☆68Nov 29, 2025Updated 6 months ago
- awesome image and video denoising, state of the art networks☆10Aug 2, 2019Updated 6 years ago
- Fault Injection Automatic Test Equipment☆15Nov 22, 2021Updated 4 years ago
- Gowin DDR3 Controller with AXI4 Implementation | 高云DDR3内存控制器AXI4接口实现☆29Mar 3, 2024Updated 2 years ago
- ☆11Sep 22, 2022Updated 3 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- [FPGA-2022] N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores☆11Dec 16, 2021Updated 4 years ago
- LVGL DEMOS STM32☆10Nov 15, 2022Updated 3 years ago
- ☆18Nov 27, 2023Updated 2 years ago
- Sparse CNN Accelerator targeting Intel FPGA☆14Aug 26, 2021Updated 4 years ago
- Models and training scripts for "LSTMs for Keyword Spotting with ReRAM-based Compute-In-Memory Architectures" (ISCAS 2021).☆17Mar 25, 2021Updated 5 years ago
- Implementation of weight stationary systolic array which has a size of 4x4(scalable) to 256X256☆31Feb 21, 2024Updated 2 years ago
- CPU implementation of the Image stitching using FAST. For FPGA implementation visit tharaka27-SocStitcher.☆12Jun 19, 2020Updated 6 years ago
- Learning Environment-aware and hardware-compatible beam-forming codebooks☆15Mar 8, 2020Updated 6 years ago
- ☆13Apr 15, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Open-source of MSD framework☆16Sep 12, 2023Updated 2 years ago
- An automated HDC platform☆11Mar 16, 2026Updated 3 months ago
- RTL code for the DPU chip designed for irregular graphs☆14May 30, 2022Updated 4 years ago
- Cryptography accelerator ASIC (for AES128/AES256 and SHA256) using Skywater 130nm process node (main project repo). Taped out in December…☆24Jan 13, 2021Updated 5 years ago
- including compiler to encode DGL GNN model to instructions, runtime software to transfer data and control the accelerator, and hardware v…☆14Nov 19, 2023Updated 2 years ago
- RDMA programming examples using Soft-RoCE☆13Aug 13, 2021Updated 4 years ago
- Extend scipy.integrate with various methods for solve_ivp☆24May 10, 2025Updated last year
- [TMLR 2024] Revisiting Random Weight Perturbation for Efficiently Improving Generalization☆12Oct 18, 2024Updated last year
- Implementation of a Systolic Array based sorting engine on an FPGA using Verilog☆11May 11, 2017Updated 9 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Implementation of YOLOv3-tiny + Depthwise Separable Convolution on FPGA☆34Mar 2, 2022Updated 4 years ago
- TCP tunnel powered by epoll☆15Dec 16, 2021Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆104Nov 26, 2025Updated 7 months ago
- ☆12Mar 11, 2024Updated 2 years ago
- HDL components to build a customized Wishbone crossbar switch☆15May 30, 2019Updated 7 years ago
- ☆41Jun 3, 2023Updated 3 years ago
- GECCO is a lightweight image classifier based on single MLP and graph convolutional layers. We find that our model can achieve up to 16x …☆11Jul 1, 2024Updated last year