PCov3r / FPGA_Handwritten_digit_recognitionLinks
A Verilog implementation of a hand-written digit recognition Neural Network
☆10Updated last year
Alternatives and similar repositories for FPGA_Handwritten_digit_recognition
Users that are interested in FPGA_Handwritten_digit_recognition are comparing it to the libraries listed below
Sorting:
- A final semester based group project for EE4218: Embedded Hardware System Design module in NUS where I worked with my teammate to perform…☆18Updated 2 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆39Updated 6 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Updated 6 years ago
- FPGA Implementation of Image Processing for MNIST Dataset Based on Convolutional Neural Network Algorithm (CNN)☆11Updated 2 years ago
- A Spiking Neuron Network Project in Verilog Implementation☆25Updated 7 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆69Updated last year
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆16Updated 3 years ago
- HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx…☆60Updated 11 months ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆36Updated 6 years ago
- EE 272B - VLSI Design Project☆13Updated 4 years ago
- Senior Design Project at UW-Madison ECE☆19Updated 2 years ago
- ☆19Updated 7 years ago
- This project is to design yolo AI accelerator in verilog HDL.☆31Updated last year
- Verilog RTL Design☆46Updated 4 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆41Updated 3 years ago
- tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.☆75Updated 2 years ago
- IEEE Transactions on Circuits and Systems I: Efficient FPGA Implementations of Pair and Triplet-based STDP for Neuromorphic Architectures☆29Updated 6 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆48Updated 2 years ago
- Spiking neural network implementation using Verilog with LIF (Leaky Integrate-and-Fire) neurons☆20Updated 5 years ago
- Single Long Short Term Memory (LSTM) cell : Verilog Implementation☆32Updated 5 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Updated 4 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆16Updated 4 years ago
- [FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.☆64Updated 4 years ago
- FPGA Design of a Spiking Neural Network.☆46Updated last year
- tpu-systolic-array-weight-stationary☆25Updated 4 years ago
- ☆30Updated 3 years ago
- A project dedicated to developing a hardware Integrated Circuit (IC) for a Spike Neural Network (SNN), powered by the RTL code generated …☆65Updated last year
- Implementation of weight stationary systolic array which has a size of 4x4(scalable) to 256X256☆28Updated last year
- Tensor Processing Unit implementation in Verilog☆13Updated 10 months ago
- EE 260 Winter 2017: Advanced VLSI Design☆68Updated 9 years ago