mnmhdanas / Router-1-x-3-Links
Router 1 x 3 verilog implementation
☆14Updated 4 years ago
Alternatives and similar repositories for Router-1-x-3-
Users that are interested in Router-1-x-3- are comparing it to the libraries listed below
Sorting:
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆10Updated 6 years ago
- UVM Testbench for synchronus fifo☆17Updated 5 years ago
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆13Updated 6 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
- Maven Silicon Project☆19Updated 6 years ago
- ☆17Updated 10 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- ☆26Updated 4 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆35Updated 2 years ago
- Verification IP for SPI protocol☆19Updated 5 years ago
- This is a open source project from UVM Community and it is based on an Ethernet Switch System-on-Chip (SoC).☆13Updated 4 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆24Updated 5 years ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆15Updated 5 months ago
- ☆20Updated 2 years ago
- ☆11Updated 3 years ago
- RTL code of some arbitration algorithm☆14Updated 6 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆17Updated 11 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆14Updated 3 years ago
- AHB/APB SRAM Inf, VCS&Verdi Sim.☆14Updated 3 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆15Updated 2 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆26Updated 7 months ago
- DDR3 function verification environment in UVM☆25Updated 7 years ago
- Design and UVM-TB of RISC -V Microprocessor☆25Updated last year
- Sample UVM code for axi ram dut☆37Updated 3 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆19Updated 7 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆20Updated 12 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆14Updated 5 years ago
- CORE-V MCU UVM Environment and Test Bench☆24Updated last year
- SoC Based on ARM Cortex-M3☆33Updated 4 months ago