mnmhdanas / Router-1-x-3-Links
Router 1 x 3 verilog implementation
☆13Updated 3 years ago
Alternatives and similar repositories for Router-1-x-3-
Users that are interested in Router-1-x-3- are comparing it to the libraries listed below
Sorting:
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆10Updated 6 years ago
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆13Updated 6 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆11Updated 4 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆14Updated last year
- UVM Testbench for synchronus fifo☆17Updated 4 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆21Updated 4 years ago
- IEEE Executive project for the year 2021-2022☆9Updated 2 years ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆10Updated 3 years ago
- Design and UVM-TB of RISC -V Microprocessor☆20Updated 11 months ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆12Updated 2 years ago
- Maven Silicon Project☆17Updated 6 years ago
- This is a open source project from UVM Community and it is based on an Ethernet Switch System-on-Chip (SoC).☆13Updated 4 years ago
- ☆25Updated 4 years ago
- ☆16Updated last year
- ☆20Updated 2 years ago
- System Verilog using Functional Verification☆12Updated last year
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆25Updated 3 years ago
- Design and verify the AMBA AXI protocol with single master-slave from scratch in System Verilog. Debugging the design using both a System…☆14Updated 7 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆16Updated 10 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- ☆14Updated 2 years ago
- CORDIC VLSI-IP for deep learning activation functions☆15Updated 5 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆22Updated 6 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆24Updated 5 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- Verification AXI-4 bus standard using UVM and System Verilog☆15Updated 7 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆11Updated 2 years ago
- ☆10Updated 4 years ago
- RTL Design and Verification☆14Updated 4 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆19Updated 12 years ago