mnmhdanas / Router-1-x-3-Links
Router 1 x 3 verilog implementation
☆14Updated 3 years ago
Alternatives and similar repositories for Router-1-x-3-
Users that are interested in Router-1-x-3- are comparing it to the libraries listed below
Sorting:
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆10Updated 6 years ago
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆13Updated 6 years ago
- UVM Testbench for synchronus fifo☆17Updated 5 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
- ☆26Updated 4 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆12Updated 5 years ago
- This is a open source project from UVM Community and it is based on an Ethernet Switch System-on-Chip (SoC).☆13Updated 4 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆35Updated 2 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- Design and UVM-TB of RISC -V Microprocessor☆25Updated last year
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆23Updated 5 years ago
- ☆17Updated 10 years ago
- Maven Silicon Project☆19Updated 6 years ago
- RTL code of some arbitration algorithm☆14Updated 6 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆24Updated 6 months ago
- ☆12Updated 9 years ago
- This project is to design yolo AI accelerator in verilog HDL.☆22Updated 10 months ago
- A 2D mesh Network on Chip with 5-stage pipelined router, all implemented in Verilog and run on Artix-7 FPGA.☆13Updated 2 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆17Updated 11 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- Verification IP for Watchdog☆11Updated 4 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆22Updated 6 years ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆14Updated 5 months ago
- verification of simple axi-based cache☆18Updated 6 years ago
- CORDIC VLSI-IP for deep learning activation functions☆15Updated 6 years ago
- uvm_axi is a uvm package for modeling and verifying AXI protocol☆18Updated 6 months ago
- Implements a simple UVM based testbench for a simple memory DUT.☆13Updated 5 years ago
- Direct Access Memory for MPSoC☆13Updated 3 months ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆15Updated last year