mvgprasanth / Systolic-Array-Matrix-MultiplicationLinks
Implementation of weight stationary systolic array which has a size of 4x4(scalable) to 256X256
☆23Updated last year
Alternatives and similar repositories for Systolic-Array-Matrix-Multiplication
Users that are interested in Systolic-Array-Matrix-Multiplication are comparing it to the libraries listed below
Sorting:
- Systolic array based simple TPU for CNN on PYNQ-Z2☆35Updated 3 years ago
- ☆34Updated 6 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆58Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated 2 weeks ago
- eyeriss-chisel3☆41Updated 3 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆39Updated last year
- ☆15Updated 2 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- Hardware accelerator for convolutional neural networks☆50Updated 3 years ago
- A final semester based group project for EE4218: Embedded Hardware System Design module in NUS where I worked with my teammate to perform…☆16Updated 2 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆50Updated 8 years ago
- This repository contains full code of Softmax Layer in Verilog☆18Updated 5 years ago
- General Purpose AXI Direct Memory Access☆57Updated last year
- Implementing Different Adder Structures in Verilog☆71Updated 5 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆11Updated last year
- This project is to design yolo AI accelerator in verilog HDL.☆22Updated 10 months ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆57Updated 10 months ago
- YSYX RISC-V Project NJU Study Group☆16Updated 7 months ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆20Updated 4 years ago
- A Spiking Neuron Network Project in Verilog Implementation☆24Updated 7 years ago
- Two Level Cache Controller implementation in Verilog HDL☆52Updated 5 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- A verilog implementation for Network-on-Chip☆76Updated 7 years ago
- Design and UVM-TB of RISC -V Microprocessor☆25Updated last year