light-ly / chisel-template
自建 chisel 工程模板
☆12Updated last year
Alternatives and similar repositories for chisel-template
Users that are interested in chisel-template are comparing it to the libraries listed below
Sorting:
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆11Updated 2 years ago
- HYF's high quality verilog codes☆13Updated 4 months ago
- ☆33Updated 6 years ago
- ☆25Updated last year
- ☆49Updated 6 years ago
- ☆19Updated 2 years ago
- ☆41Updated 3 years ago
- ☆23Updated 2 years ago
- commit rtl and build cosim env☆15Updated last year
- Open IP in Hardware Description Language.☆22Updated last year
- eyeriss-chisel3☆40Updated 3 years ago
- RTL code of some arbitration algorithm☆14Updated 5 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆37Updated 2 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆28Updated 2 years ago
- ☆10Updated 4 years ago
- Pure digital components of a UCIe controller☆62Updated this week
- verification of simple axi-based cache☆18Updated 6 years ago
- SystemVerilog modules and classes commonly used for verification☆48Updated 4 months ago
- Advanced Architecture Labs with CVA6☆59Updated last year
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆62Updated last year
- Xilinx AXI VIP example of use☆38Updated 4 years ago
- Input / Output Physical Memory Protection Unit for RISC-V☆11Updated last year
- ☆51Updated 2 years ago
- EE577b-Course-Project☆17Updated 5 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 7 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆48Updated last year
- General Purpose AXI Direct Memory Access☆49Updated last year
- ☆21Updated 5 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- Andes Vector Extension support added to riscv-dv☆16Updated 4 years ago