tharinduSamare / Multicore_processor_verilog_design
This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.
☆10Updated 3 years ago
Alternatives and similar repositories for Multicore_processor_verilog_design:
Users that are interested in Multicore_processor_verilog_design are comparing it to the libraries listed below
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 7 years ago
- Implementing Different Adder Structures in Verilog☆65Updated 5 years ago
- Design and UVM-TB of RISC -V Microprocessor☆17Updated 10 months ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- This is a verilog implementation of 4x4 systolic array multiplier☆50Updated 4 years ago
- ☆28Updated last year
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆14Updated last year
- course design☆22Updated 7 years ago
- Complete tutorial code.☆19Updated 11 months ago
- DMA Hardware Description with Verilog☆14Updated 5 years ago
- ☆19Updated 2 years ago
- CORDIC VLSI-IP for deep learning activation functions☆14Updated 5 years ago
- ☆31Updated 5 years ago
- RTL code of some arbitration algorithm☆13Updated 5 years ago
- To design test bench of the APB protocol☆17Updated 4 years ago
- Simple single-port AXI memory interface☆41Updated 10 months ago
- ☆27Updated 4 years ago
- A 32 point radix-2 FFT module written in Verilog☆23Updated 4 years ago
- ☆13Updated 2 years ago
- 异步FIFO的内部实现☆24Updated 6 years ago
- Project of an integrated UART: RTL, Verification, Physical Implementation (Innovus) and GDSII.☆10Updated 3 years ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆10Updated 5 years ago
- ☆12Updated 9 years ago
- Xilinx AXI VIP example of use☆38Updated 4 years ago
- Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.☆34Updated 10 months ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆21Updated 3 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 2 months ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆21Updated 4 years ago
- General Purpose AXI Direct Memory Access☆49Updated 11 months ago
- TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.☆17Updated last year