tharinduSamare / Multicore_processor_verilog_design
This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.
☆10Updated 3 years ago
Alternatives and similar repositories for Multicore_processor_verilog_design
Users that are interested in Multicore_processor_verilog_design are comparing it to the libraries listed below
Sorting:
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- DMA Hardware Description with Verilog☆14Updated 5 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆11Updated 2 years ago
- ☆29Updated last year
- Design and UVM-TB of RISC -V Microprocessor☆18Updated 10 months ago
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆13Updated 6 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 3 months ago
- Implementing Different Adder Structures in Verilog☆67Updated 5 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆41Updated last year
- Asynchronous fifo in verilog☆33Updated 9 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- Complete tutorial code.☆20Updated last year
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆11Updated 4 years ago
- RTL code of some arbitration algorithm☆14Updated 5 years ago
- ☆27Updated last month
- General Purpose AXI Direct Memory Access☆49Updated last year
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆17Updated last year
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆37Updated 2 years ago
- SoC Based on ARM Cortex-M3☆30Updated last week
- ☆12Updated 9 years ago
- ☆27Updated 5 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 7 years ago
- ☆19Updated 2 years ago
- APB UVC ported to Verilator☆11Updated last year
- Chisel implementation of Neural Processing Unit for System on the Chip☆21Updated this week
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆22Updated 3 months ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- commit rtl and build cosim env☆15Updated last year