Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
☆290Aug 31, 2026Updated last week
Alternatives and similar repositories for verilog-mode
Users that are interested in verilog-mode are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- verilog filetype plugin to enable emacs verilog-mode autos☆25Apr 24, 2022Updated 4 years ago
- Verilog/SystemVerilog Syntax and Omni-completion☆424Aug 3, 2026Updated last month
- Verilog Extensions for Emacs☆67Jul 16, 2026Updated last month
- verilog filetype plugin to enable emacs verilog-mode autos☆17Apr 24, 2022Updated 4 years ago
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆152Jan 23, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Verdi like, verilog code signal trace and show hierarchy script☆19Oct 16, 2019Updated 6 years ago
- automatic-verilog based on vimscript☆291Oct 24, 2023Updated 2 years ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,929Updated this week
- SystemVerilog language server☆584Aug 25, 2026Updated last week
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆116Oct 31, 2023Updated 2 years ago
- SystemVerilog linter☆391Nov 6, 2025Updated 10 months ago
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆64Jan 28, 2026Updated 7 months ago
- A set of yasnippets for emacs that assist with SystemVerilog☆11Nov 25, 2011Updated 14 years ago
- Code generation tool for control and status registers☆468Aug 16, 2026Updated 3 weeks ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- IFP (ic flow platform) is an integrated circuit design flow platform, mainly used for IC process specification management and data flow …☆208Jan 28, 2026Updated 7 months ago
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆482Jun 10, 2026Updated 2 months ago
- cocotb: Python-based chip (RTL) verification☆2,494Updated this week
- soc integration script and integration smoke script☆24Sep 12, 2022Updated 3 years ago
- SystemC/TLM-2.0 Co-simulation framework☆306Jun 26, 2026Updated 2 months ago
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆800Jun 15, 2024Updated 2 years ago
- APB4 Multiplexor☆15May 10, 2024Updated 2 years ago
- Python Tool for UVM Testbench Generation☆56May 19, 2024Updated 2 years ago
- Common SystemVerilog components☆793Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Major mode for RISC V assembly☆22Sep 16, 2022Updated 3 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,682Aug 27, 2026Updated last week
- UVM 1.2 port to Python☆262Feb 9, 2025Updated last year
- Python/Simulator integration using procedure calls☆10Mar 12, 2020Updated 6 years ago
- Novel GUI Based UVM Testbench Template Builder☆156Apr 14, 2021Updated 5 years ago
- Vim plugin for Bluespec SystemVerilog (BSV)☆12Nov 8, 2020Updated 5 years ago
- Icarus Verilog☆3,626Updated this week
- Verilator open-source SystemVerilog simulator and lint system☆3,907Updated this week
- Basic VCD comparison tool, for Verilator testing☆24Feb 24, 2026Updated 6 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Python-based IP-XACT parser and utilities☆141Jun 13, 2024Updated 2 years ago
- Filelist generator☆21Updated this week
- Using Nim to interface with SystemVerilog test benches via DPI-C☆32May 15, 2025Updated last year
- Read-only release history for Verilog-Perl☆13Jan 8, 2015Updated 11 years ago
- Embedded UVM (D Language port of IEEE UVM 1.0)☆34Nov 6, 2025Updated 10 months ago
- SystemVerilog compiler and language services☆1,130Updated this week
- Test suite designed to check compliance with the SystemVerilog standard.☆391Updated this week