Alternatives and similar repositories for verilog-mode:

Users that are interested in verilog-mode are comparing it to the libraries listed below

• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆126Updated last year
• pyuvm / pyuvm
  The UVM written in Python
  ☆402Updated last month
• gmlarumbe / verilog-ext
  Verilog Extensions for Emacs
  ☆60Updated last month
• Xilinx / XilinxTclStore
  Xilinx Tcl Store
  ☆352Updated this week
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆248Updated last week
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆378Updated 7 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆572Updated 2 weeks ago
• HonkW93 / automatic-verilog
  automatic-verilog based on vimscript
  ☆250Updated last year
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆233Updated last year
• svunit / svunit
  ☆195Updated last month
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆186Updated last year
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆521Updated 2 weeks ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆551Updated this week
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆306Updated this week
• vhda / verilog_systemverilog.vim
  Verilog/SystemVerilog Syntax and Omni-completion
  ☆374Updated 4 months ago
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆196Updated 4 months ago
• cluelogic / uvm-tutorial-for-candy-lovers
  Source code repo for UVM Tutorial for Candy Lovers
  ☆181Updated 7 years ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆473Updated 2 months ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆389Updated 5 months ago
• troyguo / awesome-dv
  Awesome ASIC design verification
  ☆285Updated 3 years ago
• funningboy / uvm_axi
  uvm AXI BFM(bus functional model)
  ☆237Updated 11 years ago
• VerificationExcellence / UVMReference
  Reference examples and short projects using UVM Methodology
  ☆257Updated 2 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-Step-By-Step
  This is the main repository for all the examples for the book Practical UVM
  ☆182Updated 4 years ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆777Updated 6 months ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆300Updated 9 months ago
• raysalemi / uvmprimer
  Contains the code examples from The UVM Primer Book sorted by chapters.
  ☆511Updated 3 years ago
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆88Updated last year
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆264Updated 4 years ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆143Updated 2 years ago
• rggen / rggen
  Code generation tool for control and status registers
  ☆363Updated this week