Alternatives and similar repositories for verilog-mode

Users that are interested in verilog-mode are comparing it to the libraries listed below

• pyuvm / pyuvm
  The UVM written in Python
  ☆434Updated this week
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆136Updated last year
• rggen / rggen
  Code generation tool for control and status registers
  ☆397Updated 3 weeks ago
• Xilinx / XilinxTclStore
  Xilinx Tcl Store
  ☆359Updated 3 weeks ago
• cluelogic / uvm-tutorial-for-candy-lovers
  Source code repo for UVM Tutorial for Candy Lovers
  ☆189Updated 8 years ago
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆405Updated 11 months ago
• svunit / svunit
  ☆201Updated 3 months ago
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆199Updated 8 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆629Updated this week
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆252Updated 4 months ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆267Updated last year
• gmlarumbe / verilog-ext
  Verilog Extensions for Emacs
  ☆61Updated 3 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆582Updated 2 weeks ago
• VerificationExcellence / UVMReference
  Reference examples and short projects using UVM Methodology
  ☆273Updated 3 years ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆207Updated last year
• HonkW93 / automatic-verilog
  automatic-verilog based on vimscript
  ☆266Updated last year
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆353Updated last year
• funningboy / uvm_axi
  uvm AXI BFM(bus functional model)
  ☆248Updated 12 years ago
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆101Updated last year
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆328Updated this week
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆254Updated 3 months ago
• cluelogic / cluelib
  A generic class library in SystemVerilog
  ☆84Updated 4 years ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆269Updated 4 years ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆149Updated 3 months ago
• thomasrussellmurphy / stx_cookbook
  Altera Advanced Synthesis Cookbook 11.0
  ☆104Updated 2 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-Step-By-Step
  This is the main repository for all the examples for the book Practical UVM
  ☆196Updated 4 years ago
• imc-trading / svlangserver
  ☆111Updated last year
• VerificationExcellence / SystemVerilogReference
  training labs and examples
  ☆424Updated 2 years ago
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆141Updated 4 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆568Updated 2 months ago