Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
☆289Sep 30, 2026Updated 2 weeks ago
Alternatives and similar repositories for verilog-mode
Users that are interested in verilog-mode are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- verilog filetype plugin to enable emacs verilog-mode autos☆25Apr 24, 2022Updated 4 years ago
- Verilog/SystemVerilog Syntax and Omni-completion☆424Aug 3, 2026Updated 2 months ago
- Verilog Extensions for Emacs☆67Sep 16, 2026Updated last month
- verilog filetype plugin to enable emacs verilog-mode autos☆17Apr 24, 2022Updated 4 years ago
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆152Jan 23, 2024Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Verdi like, verilog code signal trace and show hierarchy script☆19Oct 16, 2019Updated 7 years ago
- automatic-verilog based on vimscript☆292Oct 24, 2023Updated 2 years ago
- SystemVerilog language server☆586Sep 14, 2026Updated last month
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,959Sep 23, 2026Updated 3 weeks ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆116Oct 31, 2023Updated 2 years ago
- SystemVerilog linter☆393Nov 6, 2025Updated 11 months ago
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆64Oct 7, 2026Updated last week
- A set of yasnippets for emacs that assist with SystemVerilog☆11Nov 25, 2011Updated 14 years ago
- Code generation tool for control and status registers☆471Sep 11, 2026Updated last month
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- IFP (ic flow platform) is an integrated circuit design flow platform, mainly used for IC process specification management and data flow …☆209Jan 28, 2026Updated 8 months ago
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆482Jun 10, 2026Updated 4 months ago
- cocotb: Python-based chip (RTL) verification☆2,544Updated this week
- soc integration script and integration smoke script☆24Sep 12, 2022Updated 4 years ago
- SystemC/TLM-2.0 Co-simulation framework☆310Jun 26, 2026Updated 3 months ago
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆802Jun 15, 2024Updated 2 years ago
- APB4 Multiplexor☆15May 10, 2024Updated 2 years ago
- Python Tool for UVM Testbench Generation☆57May 19, 2024Updated 2 years ago
- Common SystemVerilog components☆808Sep 18, 2026Updated 3 weeks ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,724Sep 24, 2026Updated 3 weeks ago
- Major mode for RISC V assembly☆22Sep 16, 2022Updated 4 years ago
- UVM 1.2 port to Python☆262Feb 9, 2025Updated last year
- Python/Simulator integration using procedure calls☆10Mar 12, 2020Updated 6 years ago
- Novel GUI Based UVM Testbench Template Builder☆156Apr 14, 2021Updated 5 years ago
- Vim plugin for Bluespec SystemVerilog (BSV)☆12Nov 8, 2020Updated 5 years ago
- Icarus Verilog☆3,683Updated this week
- Verilator open-source SystemVerilog simulator and lint system☆4,015Updated this week
- Basic VCD comparison tool, for Verilator testing☆24Feb 24, 2026Updated 7 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Python-based IP-XACT parser and utilities☆142Jun 13, 2024Updated 2 years ago
- Filelist generator☆21Sep 14, 2026Updated last month
- Using Nim to interface with SystemVerilog test benches via DPI-C☆32May 15, 2025Updated last year
- Read-only release history for Verilog-Perl☆14Jan 8, 2015Updated 11 years ago
- Embedded UVM (D Language port of IEEE UVM 1.0)☆34Nov 6, 2025Updated 11 months ago
- SystemVerilog compiler and language services☆1,164Updated this week
- Test suite designed to check compliance with the SystemVerilog standard.☆400Updated this week