daeyeon22 / artificial_netlist_generatorLinks
Artificial Netlist Generator
☆44Updated last year
Alternatives and similar repositories for artificial_netlist_generator
Users that are interested in artificial_netlist_generator are comparing it to the libraries listed below
Sorting:
- Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)☆82Updated last year
- Analog IC symmetry extraction benchmark of AncstrGNN☆10Updated last year
- ☆62Updated 2 weeks ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆58Updated 10 months ago
- Collection of digital hardware modules & projects (benchmarks)☆69Updated last week
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆136Updated 3 months ago
- ☆31Updated 3 years ago
- This GitHub repo is for the OpenROAD and CircuitOps Tutorial at ASP-DAC 2024☆52Updated 10 months ago
- ☆23Updated last year
- ☆18Updated 4 years ago
- Rsyn – An Extensible Physical Synthesis Framework☆132Updated last year
- Analog Placement Quality Prediction☆25Updated 2 years ago
- ☆31Updated 2 years ago
- Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".☆55Updated 5 months ago
- Machine Generated Analog IC Layout☆259Updated last year
- CUGR, VLSI Global Routing Tool Developed by CUHK☆138Updated 2 years ago
- ☆27Updated last year
- ☆76Updated 5 months ago
- DATC RDF☆50Updated 5 years ago
- the awesome work, project and lab of EDA (Electronic Design Automation). continue update...☆24Updated last year
- GNN-RE datasets for circuit recognition☆55Updated 2 years ago
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆35Updated 4 months ago
- ☆89Updated 4 months ago
- ☆49Updated last year
- Open Source Detailed Placement engine☆39Updated 5 years ago
- ☆94Updated 3 months ago
- ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino☆65Updated 6 months ago
- GPU-based logic synthesis tool☆93Updated this week
- Hypergraph Partitioning: benchmarks, evaluators, best known solutions and codes☆75Updated 3 weeks ago
- ☆47Updated last year