Alternatives and similar repositories for Deep-Learning-For-Analog-Circuit-Sizing

Users that are interested in Deep-Learning-For-Analog-Circuit-Sizing are comparing it to the libraries listed below

• patrickschulz / openPCells
  Parametric layout generator for digital, analog and mixed-signal integrated circuits
  ☆56Updated last week
• sgherbst / msdsl
  Automatic generation of real number models from analog circuits
  ☆43Updated last year
• USCPOSH / AMPSE
  This is the repository of IPs of the group in USC who is developing Analog Mixed-signal Parameter Search Engine (AMPSE). You can download…
  ☆25Updated 2 years ago
• AyarLabs / ACG
  Arbitrary Cell Generator enables parametrized grid-free circuit layout creation
  ☆15Updated 5 years ago
• jimwang99 / parser-for-chip-design
  A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).
  ☆32Updated 10 years ago
• ALIGN-analoglayout / AnalogDetailedRouter
  Intel's Analog Detailed Router
  ☆39Updated 6 years ago
• electronics-and-drives / MLCAD22
  Source code for the Paper: "Deep Reinforcement Learning for Analog Circuit Sizing with an Electrical Design Space and Sparse Rewards"
  ☆13Updated 3 years ago
• ucb-art / laygo
  LAYout with Gridded Objects
  ☆29Updated 5 years ago
• purdue-onchip / gds2Para
  GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
  ☆124Updated 2 years ago
• ChrisZonghaoLi / sky130_ldo_rl
  This repo contains the code that runs RL+GNN to optimize LDOs in SKY130 process.
  ☆41Updated last year
• magical-eda / MAGICAL-CIRCUITS
  Circuit release of the MAGICAL project
  ☆38Updated 5 years ago
• sgherbst / sky130-hello-world
  Minimal SKY130 example with self-checking LVS, DRC, and PEX
  ☆23Updated 4 years ago
• aolofsson / IDEA
  ☆33Updated 5 years ago
• AvestimehrResearchGroup / AICircuit
  The implementation of AICircuit: A Multi-Level Dataset and Benchmark for AI-Driven Analog Integrated Circuit Design
  ☆68Updated 7 months ago
• ABKGroup / PROBE3.0
  ☆45Updated last year
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆61Updated last year
• niftylab / laygo2
  LAYout with Gridded Objects v2
  ☆63Updated 2 months ago
• cogenda / VA-BSIM48
  Verilog-A implementation of MOSFET model BSIM4.8
  ☆14Updated 5 years ago
• OpenROAD-Assistant / EDA-Corpus
  Datasets for EDA LLM research
  ☆33Updated 8 months ago
• peaclab / PACT
  PACT: A Parallel Compact Thermal Simulator
  ☆53Updated last week
• muhammadaldacher / Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOS
  This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.
  ☆24Updated 6 years ago
• muhammadaldacher / Analog-Design-of-1.5-bit-Pipeline-ADC-And-Boosted-OpAmp
  This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.
  ☆34Updated 3 years ago
• ieee-ceda-datc / datc-rdf-Metrics4ML
  ☆31Updated 3 years ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆30Updated last year
• ashwith / pyMOSChar
  Python port of Prof. Boris Murmann's gm/ID Starter Kit
  ☆54Updated 8 years ago
• aolofsson / POSH
  ☆44Updated 5 years ago
• vsdip / vsdStdCellCharacterizer_sky130
  ☆20Updated 3 years ago
• bluecheetah / bag
  BAG framework
  ☆41Updated last year
• ckchengucsd / SMT-based-STDCELL-Layout-Generator
  SMT-based-STDCELL-Layout-Generator
  ☆18Updated 3 years ago
• gdsfactory / skywater130
  skywater 130nm pdk
  ☆34Updated this week