JinwooWang / Deep-Learning-For-Analog-Circuit-SizingLinks
Combination of Analog Circuit Sizing and DL.
☆17Updated 2 years ago
Alternatives and similar repositories for Deep-Learning-For-Analog-Circuit-Sizing
Users that are interested in Deep-Learning-For-Analog-Circuit-Sizing are comparing it to the libraries listed below
Sorting:
- Automatic generation of real number models from analog circuits☆42Updated last year
- This is the repository of IPs of the group in USC who is developing Analog Mixed-signal Parameter Search Engine (AMPSE). You can download…☆25Updated 2 years ago
- Parametric layout generator for digital, analog and mixed-signal integrated circuits☆56Updated this week
- Arbitrary Cell Generator enables parametrized grid-free circuit layout creation☆15Updated 5 years ago
- Circuit release of the MAGICAL project☆35Updated 5 years ago
- This repo contains the code that runs RL+GNN to optimize LDOs in SKY130 process.☆38Updated last year
- Source code for the Paper: "Deep Reinforcement Learning for Analog Circuit Sizing with an Electrical Design Space and Sparse Rewards"☆13Updated 2 years ago
- Intel's Analog Detailed Router☆39Updated 6 years ago
- SMT-based-STDCELL-Layout-Generator☆18Updated 3 years ago
- skywater 130nm pdk☆31Updated last week
- A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).☆32Updated 10 years ago
- LAYout with Gridded Objects☆29Updated 5 years ago
- ☆33Updated 5 years ago
- ☆20Updated 3 years ago
- Reinforcement learning assisted analog layout design flow.☆24Updated last year
- The implementation of AICircuit: A Multi-Level Dataset and Benchmark for AI-Driven Analog Integrated Circuit Design☆64Updated 6 months ago
- Skywater 130nm Klayout Device Generators PDK☆31Updated last year
- Design of Analog Blocks in Skywaters 130nm meeting corners: different flavors of OTA, BandGap, LDO.☆27Updated 3 years ago
- Verilog-A implementation of MOSFET model BSIM4.8☆14Updated 5 years ago
- Datasets for EDA LLM research☆32Updated 6 months ago
- GDSII File Parsing, IC Layout Analysis, and Parameter Extraction☆121Updated 2 years ago
- Python package for IBIS-AMI model development and testing☆29Updated 2 weeks ago
- A RRAM addon for the NCSU FreePDK 45nm☆23Updated 3 years ago
- ☆31Updated 3 years ago
- ☆34Updated 2 years ago
- Open source process design kit for 28nm open process☆60Updated last year
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆23Updated 4 years ago
- Open Source PHY v2☆29Updated last year
- ☆44Updated 5 years ago
- Hardware Description Library☆82Updated 3 months ago