Maxpicca-Li / CDIMLinks
CQU Dual Issue Machine
☆35Updated last year
Alternatives and similar repositories for CDIM
Users that are interested in CDIM are comparing it to the libraries listed below
Sorting:
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆49Updated last year
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆49Updated 8 months ago
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆81Updated last year
- 第六届龙芯杯混元形意太极门战队作品☆18Updated 3 years ago
- Linux-capable out-of-order superscaler multicore LoongArch32 (LA32 / LA32R) processor.☆26Updated 11 months ago
- gem5 FS模式实验手册☆43Updated 2 years ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆51Updated 2 years ago
- LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. (第五届龙芯杯特等奖作…☆36Updated 3 years ago
- "aura" my super-scalar O3 cpu core☆24Updated last year
- Mirror of https://gitee.com/loongson-edu/open-la500.git☆18Updated 6 months ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆42Updated 11 months ago
- ☆39Updated this week
- 给NEMU移植Linux Kernel!☆18Updated last month
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆39Updated 2 years ago
- ☆19Updated 11 months ago
- This is an IDE for YSYX_NPC debuging☆12Updated 7 months ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆62Updated 3 years ago
- This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…☆16Updated 9 months ago
- Pick your favorite language to verify your chip.☆51Updated this week
- ☆27Updated 5 months ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆31Updated 3 months ago
- ☆11Updated 4 months ago
- SystemVerilog implemention of the TAGE branch predictor☆12Updated 4 years ago
- SoC for CQU Dual Issue Machine☆12Updated 2 years ago
- Introduction to Computer Systems (II), Spring 2021☆51Updated 4 years ago
- GPGPU-Sim 中文注释版代码,包含 GPGPU-Sim 模拟器的最新版代码,经过中文注释,以帮助中文用户更好地理解和使用该模拟器。☆19Updated 6 months ago
- Xiangshan deterministic workloads generator☆19Updated last month
- A Study of the SiFive Inclusive L2 Cache☆65Updated last year
- ☆35Updated last year