ProjectDimlight / SOL-s-Verilog-Cheatsheet-for-Not-So-Beginners
☆22Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for SOL-s-Verilog-Cheatsheet-for-Not-So-Beginners
- 体系结构研讨 + ysyx高阶 大纲 (WIP☆116Updated last month
- 龙芯杯21个人赛作品☆34Updated 3 years ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆43Updated 2 weeks ago
- ☆60Updated 3 months ago
- A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …☆107Updated 3 weeks ago
- Unofficial guide for ysyx students applying to ShanghaiTech University☆16Updated 4 months ago
- ☆76Updated 2 months ago
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆121Updated 4 months ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆25Updated 7 months ago
- 复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品☆40Updated 4 years ago
- A softcore microprocessor of MIPS32 architecture.☆39Updated 4 months ago
- 适用于龙芯杯团队赛入门选手的应急cache模块☆22Updated 8 months ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated 8 months ago
- 一生一芯的信息发布和内容网站☆123Updated last year
- verilog module add prefix script 可用于ysyx项目添加学号☆13Updated 8 months ago
- NJU Virtual Board☆235Updated 3 months ago
- 龙芯杯个人赛工具包（适用于个人赛的golden_trace工具）☆48Updated 8 months ago
- ☆33Updated 5 years ago
- Asymmetric dual issue in-order microprocessor.☆34Updated 5 years ago
- ☆43Updated 4 months ago
- ☆31Updated last year
- Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022☆9Updated 2 years ago
- Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.☆162Updated 3 years ago
- ☆20Updated last month
- 为了更好地帮助后来的同学参加龙芯杯，草拟了这份建议，望对后来人有所帮助☆114Updated 4 years ago
- ☆20Updated 11 months ago
- ☆63Updated 2 years ago
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆45Updated 11 months ago
- ☆14Updated 2 years ago
- ☆119Updated 2 months ago