LainChip / LainCoreLinks
Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
☆45Updated last year
Alternatives and similar repositories for LainCore
Users that are interested in LainCore are comparing it to the libraries listed below
Sorting:
- Linux-capable out-of-order superscaler multicore LoongArch32 (LA32 / LA32R) processor.☆32Updated last year
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Updated 3 years ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆49Updated last month
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated 2 weeks ago
- CQU Dual Issue Machine☆37Updated last year
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆82Updated 2 years ago
- A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …☆118Updated last year
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆40Updated 2 years ago
- "aura" my super-scalar O3 cpu core☆24Updated last year
- The 'missing header' for Chisel☆21Updated 7 months ago
- Run Rocket Chip on VCU128☆30Updated 3 weeks ago
- ☆20Updated last year
- ☆35Updated 2 years ago
- Pick your favorite language to verify your chip.☆73Updated last week
- LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…☆37Updated 3 years ago
- 给NEMU移植Linux Kernel!☆21Updated 5 months ago
- ☆62Updated last month
- 龙芯杯21个人赛作品☆36Updated 4 years ago
- Modern co-simulation framework for RISC-V CPUs☆159Updated this week
- Implements kernels with RISC-V Vector☆22Updated 2 years ago
- Crowdsourced Verification Project (UnityChip Verification) for the Xiangshan Processor☆45Updated 2 weeks ago
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆49Updated last year
- A fork of Xiangshan for AI☆33Updated this week
- A docker image for One Student One Chip's debug exam☆11Updated 2 years ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆31Updated 7 months ago
- Mirror of https://gitee.com/loongson-edu/open-la500.git☆18Updated 10 months ago
- Unofficial guide for ysyx students applying to ShanghaiTech University☆23Updated 8 months ago
- 本项目已被合并至官方Chiplab中☆12Updated 10 months ago
- ☆68Updated 9 months ago
- 第六届龙芯杯混元形意太极门战队作品☆18Updated 3 years ago