LainChip / LainCore
Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
☆38Updated 6 months ago
Alternatives and similar repositories for LainCore:
Users that are interested in LainCore are comparing it to the libraries listed below
- Linux-capable out-of-order superscaler multicore LoongArch32 (LA32 / LA32R) processor.☆18Updated 6 months ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated 11 months ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆46Updated 3 months ago
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆74Updated last year
- The 'missing header' for Chisel☆18Updated this week
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆38Updated last year
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆56Updated 3 years ago
- ☆15Updated 6 months ago
- Run Rocket Chip on VCU128☆29Updated 2 months ago
- ☆32Updated last year
- 龙芯杯21个人赛作品☆34Updated 3 years ago
- ☆59Updated 2 weeks ago
- "aura" my super-scalar O3 cpu core☆24Updated 8 months ago
- 第六届龙芯杯混元形意太极门战队作品☆17Updated 2 years ago
- A Flexible Cache Architectural Simulator☆13Updated 2 months ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆28Updated 10 months ago
- This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…☆14Updated 4 months ago
- The experimental work to rewrite Chisel in pure Scala 3 and the Panama Project☆24Updated this week
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆46Updated last year
- hardware & software prefetcher☆23Updated last year
- ☆32Updated this week
- ☆17Updated 2 years ago
- Implements kernels with RISC-V Vector☆21Updated last year
- A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …☆111Updated 3 months ago
- Modern co-simulation framework for RISC-V CPUs☆133Updated this week
- Lower chisel memories to SRAM macros☆12Updated 10 months ago
- A small RISC-V kernel coding by C, tested on sifive unmatched board.☆16Updated 2 years ago
- CQU Dual Issue Machine☆35Updated 7 months ago
- ☆17Updated last year
- Open source high performance IEEE-754 floating unit☆67Updated 11 months ago