cyyself / cyyrv64Links
My RV64 CPU (Work in progress)
☆19Updated 2 years ago
Alternatives and similar repositories for cyyrv64
Users that are interested in cyyrv64 are comparing it to the libraries listed below
Sorting:
- The MIPS CPU from previous CQU NSCSCC team and debugged by me running uCore MIPS porting successfully☆9Updated 4 years ago
- Implements kernels with RISC-V Vector☆22Updated 2 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆62Updated 3 years ago
- This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…☆21Updated 4 months ago
- Run Rocket Chip on VCU128☆30Updated 7 months ago
- What if everything is a io_uring?☆16Updated 2 years ago
- User-mode trap-and-emulate hypervisor for RISC-V☆13Updated 3 years ago
- The 'missing header' for Chisel☆20Updated 3 months ago
- A Symmetric Multiprocessing OS Kernel over RISC-V☆31Updated 3 years ago
- Lower chisel memories to SRAM macros☆12Updated last year
- RV32I by cats☆16Updated last year
- (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog☆12Updated 3 years ago
- A hand-written recursive decent Verilog parser.☆11Updated 2 years ago
- My knowledge base☆62Updated last week
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆42Updated 11 months ago
- Backend & Frontend for JieLabs☆22Updated 2 years ago
- Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards☆19Updated 7 months ago
- An SoC with multiple RISC-V IMA processors.☆19Updated 6 years ago
- A hardware accelerated IP packet forwarder running on programmable ICs☆16Updated 2 years ago
- Paging Debug tool for GDB using python☆13Updated 3 years ago
- Open-source RISC-V cryptographic hardware token, RTL repo☆19Updated 2 years ago
- ☆17Updated 3 years ago
- A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …☆117Updated 8 months ago
- A 3d printed case design for Lichee Pi 4A☆12Updated 2 years ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆49Updated 8 months ago
- WIP: A fork of OpenSBI, with software-emulated hypervisor extension support☆39Updated 4 months ago
- Documentation for Digital Design course☆20Updated last month
- Recommended coding standard of Verilog and SystemVerilog.☆34Updated 3 years ago
- Wrappers for open source FPU hardware implementations.☆32Updated last year
- uCore MIPS32 porting☆18Updated 5 years ago