Alternatives and similar repositories for cyyrv64

Users that are interested in cyyrv64 are comparing it to the libraries listed below

• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆61Updated 3 years ago
• dramforever / urvirt
  User-mode trap-and-emulate hypervisor for RISC-V
  ☆13Updated 3 years ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 10 months ago
• CircuitCoder / ChannelOS
  What if everything is a io_uring?
  ☆16Updated 2 years ago
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆44Updated last year
• jiegec / verilog-lang
  A hand-written recursive decent Verilog parser.
  ☆10Updated 3 years ago
• dramforever / ixayoi
  (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog
  ☆12Updated 4 years ago
• riscv / riscv-control-transfer-records
  This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…
  ☆23Updated 7 months ago
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆21Updated 6 months ago
• Oyami-Srk / RISCV-GDB-Paging
  Paging Debug tool for GDB using python
  ☆13Updated 3 years ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆34Updated last year
• comparch-security / chipyard-random-llc
  A Rocket-Chip with a Dynamically Randomized LLC
  ☆13Updated last year
• OpenRigil / openrigil-rtl
  Open-source RISC-V cryptographic hardware token, RTL repo
  ☆19Updated 2 years ago
• char-fish-after-lunch / SystemOnCat
  An SoC with multiple RISC-V IMA processors.
  ☆19Updated 7 years ago
• thu-cs-lab / JieLabs-Web
  Backend & Frontend for JieLabs
  ☆22Updated 2 years ago
• z4yx / vivado-docker
  Dockerfile with Vivado for CI
  ☆27Updated 5 years ago
• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆12Updated last year
• cnrv / RVWC2021-slides
  第一届 RISC-V 中国峰会的幻灯片等资料存放
  ☆38Updated 2 years ago
• cyyself / cemu
  A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …
  ☆118Updated 11 months ago
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆37Updated last year
• TianhuaTao / uCore-SMP
  A Symmetric Multiprocessing OS Kernel over RISC-V
  ☆32Updated 3 years ago
• monkey2000 / LPi4A-Case
  A 3d printed case design for Lichee Pi 4A
  ☆12Updated 2 years ago
• CircuitCoder / mill
  RV32I by cats
  ☆16Updated 2 years ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆49Updated last week
• jiegec / kb
  My knowledge base
  ☆67Updated 2 weeks ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• cyyself / CDIM-SoC
  SoC for CQU Dual Issue Machine
  ☆12Updated 3 years ago
• AlwenXXD / nscscc2021
  龙芯杯21个人赛作品
  ☆35Updated 4 years ago
• MaxXSoft / Bossa
  BOOM's Simulation Accelerator.
  ☆14Updated 3 years ago