fluctlight001 / cpu_for_nscscc2022_single
2022年龙芯杯个人赛 单发射110M(含icache)
☆44Updated 2 years ago
Alternatives and similar repositories for cpu_for_nscscc2022_single:
Users that are interested in cpu_for_nscscc2022_single are comparing it to the libraries listed below
- 龙芯杯个人赛工具包(适用于个人赛的golden_trace工具)☆48Updated last year
- 2020龙芯杯个人赛 简易双发射60M(含ibuffer)☆35Updated 4 years ago
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆128Updated 8 months ago
- 适用于龙芯杯团队赛入门选手的应急cache模块☆23Updated last year
- 2022龙芯杯个人赛三等奖作品☆13Updated last year
- 复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品☆42Updated 4 years ago
- ☆33Updated last year
- NSCSCC2022龙芯杯个人赛,MIPS32,59MHz经典五级流水线架构,易于初学者阅读(计算机组成原理,自己动手写CPU)☆60Updated last year
- ☆62Updated 7 months ago
- NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.☆11Updated 11 months ago
- 为了更好地帮助后来的同学参加龙芯杯,草拟了这份建议,望对后来人有所帮助☆122Updated 4 years ago
- 龙芯杯21个人赛作品☆34Updated 3 years ago
- ☆17Updated 7 months ago
- verilog module add prefix script 可用于ysyx项目添加学号☆13Updated last year
- NSCSCC 信息整合☆233Updated 4 years ago
- 2023龙芯杯mips赛道作品☆11Updated last year
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆38Updated last year
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆76Updated last year
- 体系结构研讨 + ysyx高阶大纲 (WIP☆145Updated 5 months ago
- ☆61Updated last year
- A classic five stage pipelined processor☆13Updated last year
- ☆58Updated 2 months ago
- This is my graduation project, a simple processor soft core, which implements RV32I ISA.☆15Updated 5 years ago
- ☆79Updated last month
- "aura" my super-scalar O3 cpu core☆24Updated 9 months ago
- NSCSCC 2020 - Yet Another MIPS Processor☆14Updated 3 years ago
- A LoongArch pipeline CPU. Project of Computer Architecture Lab @UCAS.☆21Updated 9 months ago
- riscv指令集,单周期以及五级流水线CPU☆45Updated 2 months ago
- ☆139Updated 6 months ago
- NJU ICS课程的PA实验,非常棒的一个大项目,受益匪浅!一栈式打通虚拟机NEMU、操作系统NLiteOS和应用层☆47Updated 2 years ago