HIT-MaRiver-mips / cpucore-mariverView external linksLinks
☆35Aug 22, 2023Updated 2 years ago
Alternatives and similar repositories for cpucore-mariver
Users that are interested in cpucore-mariver are comparing it to the libraries listed below
Sorting:
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆83Aug 29, 2023Updated 2 years ago
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆40Jul 4, 2023Updated 2 years ago
- This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…☆17Sep 29, 2024Updated last year
- Second Prize in NSCSCC 2024. An out-of-order CPU designed by NoAXI team from HDU. 2024年全国大学生计算机系统能力大赛CPU设计赛(龙芯杯)团队赛二等奖作品☆23Sep 14, 2024Updated last year
- ☆22Aug 11, 2024Updated last year
- NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.☆13Mar 29, 2025Updated 10 months ago
- ☆17Jun 24, 2024Updated last year
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆45Jul 25, 2024Updated last year
- nscscc2024,HPU河南理工大学参赛作品,两仪处理器☆11Aug 24, 2024Updated last year
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆32Apr 13, 2025Updated 10 months ago
- Linux-capable out-of-order superscaler multicore LoongArch32 (LA32 / LA32R) processor.☆32Aug 9, 2024Updated last year
- 乱序双发处理器,在2024年计算机系统能力大赛CPU赛道(龙芯杯)获二等奖,全国第四☆18Aug 20, 2024Updated last year
- ☆14Nov 23, 2020Updated 5 years ago
- 适用于龙芯杯团队赛入门选手的应急cache模块☆30Mar 13, 2024Updated last year
- 体系结构研讨 + ysyx高阶大纲 (WIP☆197Oct 14, 2024Updated last year
- 顺序单/双发射LA32R处理器 (龙芯杯2024) A LA32R CPU in chisel☆25Jan 25, 2026Updated 3 weeks ago
- Build mini linux for your own RISC-V emulator!☆23Sep 11, 2024Updated last year
- A Flexible Cache Architectural Simulator☆16Sep 16, 2025Updated 5 months ago
- Falcon: Fast OLTP Engine for Persistent Cache and Non-Volatile Memory☆11Nov 1, 2023Updated 2 years ago
- "aura" my super-scalar O3 cpu core☆25May 25, 2024Updated last year
- 2022龙芯杯个人赛三等奖作品☆14Oct 11, 2023Updated 2 years ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆51Dec 18, 2025Updated last month
- ☆10Sep 23, 2025Updated 4 months ago
- Vivado in GitLab-Runner for GitLab CI/CD☆10Oct 27, 2022Updated 3 years ago
- CPU source code for NSCSCC 2023☆14Aug 26, 2023Updated 2 years ago
- 本项目已被合并至官方Chiplab中☆13Jan 13, 2025Updated last year
- About the source code of "Merging Similar Patterns for Hardware Prefetching" paper, which is accepted in MICRO 2022.☆14Mar 1, 2023Updated 2 years ago
- Documentation for XiangShan Design☆42Feb 3, 2026Updated 2 weeks ago
- CQU Dual Issue Machine☆38Jun 23, 2024Updated last year
- ☆21May 30, 2025Updated 8 months ago
- 给NEMU移植Linux Kernel!☆22Jun 1, 2025Updated 8 months ago
- Run wavedrom in typst☆18Apr 9, 2025Updated 10 months ago
- A riscv emulator.☆19Feb 5, 2024Updated 2 years ago
- CPU敏捷开发框架(龙芯杯2024)☆25Sep 6, 2024Updated last year
- A Portable Linux-based Firmware for NVMe Computational Storage Devices☆31Jun 10, 2025Updated 8 months ago
- Source code for COLING 2022 paper "Automatic Label Sequence Generation for Prompting Sequence-to-sequence Models"☆24Sep 21, 2022Updated 3 years ago
- ☆15Mar 29, 2023Updated 2 years ago
- Open-source non-blocking L2 cache☆52Updated this week
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆25Nov 26, 2025Updated 2 months ago