saivittalb / branch-prediction-programmingLinks
🎞 Implementation of several Branch Prediction algorithms and analysis on their effectiveness on real-world program traces.
☆21Updated 4 years ago
Alternatives and similar repositories for branch-prediction-programming
Users that are interested in branch-prediction-programming are comparing it to the libraries listed below
Sorting:
- SystemVerilog implemention of the TAGE branch predictor☆13Updated 4 years ago
- gem5 FS模式实验手册☆45Updated 2 years ago
- This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…☆17Updated last year
- A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.☆15Updated 3 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆62Updated 4 years ago
- ☆11Updated last year
- Verilog Implementation of TAGE based predictor by Andre Seznec and Pierre Michaud☆21Updated 7 years ago
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆50Updated 2 years ago
- An almost empty chisel project as a starting point for hardware design☆33Updated 11 months ago
- ☆32Updated 5 months ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆33Updated last year
- CQU Dual Issue Machine☆38Updated last year
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆31Updated this week
- Xiangshan deterministic workloads generator☆24Updated 7 months ago
- Advanced Architecture Labs with CVA6☆72Updated last year
- ☆22Updated 2 years ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆51Updated 3 weeks ago
- GPGPU-Sim 中文注释版代码,包含 GPGPU-Sim 模拟器的最新版代码,经过中文注释,以帮助中文用户更好地理解和使用该模拟器。☆28Updated last year
- ☆52Updated 11 months ago
- Implementing the Precise Runahead (HPCA'20) in gem5☆13Updated 2 years ago
- "aura" my super-scalar O3 cpu core☆24Updated last year
- ☆65Updated 3 years ago
- ☆122Updated this week
- Lab assignments for the Agile Hardware Design course☆17Updated last month
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆47Updated 6 months ago
- SystemC training aimed at TLM.☆34Updated 5 years ago
- ☆70Updated 11 months ago
- A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…☆76Updated 4 months ago
- A docker image for One Student One Chip's debug exam☆10Updated 2 years ago
- Running ahead of memory latency - Part II project☆10Updated 3 years ago