๐ Implementation of several Branch Prediction algorithms and analysis on their effectiveness on real-world program traces.
โ21Apr 10, 2021Updated 5 years ago
Alternatives and similar repositories for branch-prediction-programming
Users that are interested in branch-prediction-programming are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Branch predictor simulation, analysis, and Python compatibility for the 5th Championship Branch Prediction in 2016 (CBP-16)โ22Mar 9, 2023Updated 3 years ago
- Super scalar Processor designโ21Sep 7, 2014Updated 11 years ago
- A branch predictor simulator in C++ that tests 6 different types of branch predictors.โ13Apr 26, 2018Updated 8 years ago
- Paging Debug tool for GDB using pythonโ13Jun 4, 2022Updated 4 years ago
- A MIPS processor with Cache and Advanced Branch Predictor written in SystemVerilogโ11Dec 26, 2020Updated 5 years ago
- Managed Database hosting by DigitalOcean โข AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Implementation of a cache memory in verilogโ15Dec 5, 2017Updated 8 years ago
- HITsz LUG ๅจๆฅโ21Jul 11, 2023Updated 3 years ago
- SystemVerilog implemention of the TAGE branch predictorโ14May 26, 2021Updated 5 years ago
- Implementation of Direct-Mapped-Cache to hold 256 blocks, 16 32-bit instruction/Data per block with 32-bit address lineโ15Dec 29, 2018Updated 7 years ago
- Artifact of "Indirector: High-Precision Branch Target Injection Attacks Exploiting the Indirect Branch Predictor" [USENIX Security 2024]โ61May 28, 2026Updated 2 months ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.โ52Mar 31, 2026Updated 4 months ago
- LRU-Cache-using-Cโ14Mar 25, 2018Updated 8 years ago
- A simple MIPS Simulator that can simulate execution in MIPS for a small subset of instructions under several restrictionsโ10Sep 10, 2019Updated 6 years ago
- General Purpose Graphics Processing Unit (GPGPU) IP Coreโ11Jul 4, 2014Updated 12 years ago
- Managed Kubernetes at scale on DigitalOcean โข AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- โ19Mar 8, 2025Updated last year
- Verilog Implementation of TAGE based predictor by Andre Seznec and Pierre Michaudโ22May 7, 2018Updated 8 years ago
- Repository of HITSZ OSA Wikiโ42Jul 21, 2026Updated 3 weeks ago
- Simulator that maintains coherent caches for 4, 8 and 16 core CMP. Implementation of MSI, MESI, MOSI, MOESI and MOESIF protocols for a bโฆโ11Jan 6, 2015Updated 11 years ago
- parse device tree blobsโ18Apr 16, 2026Updated 3 months ago
- ๆๆกฃ็ผๅโ14Sep 19, 2020Updated 5 years ago
- Computer Architecture UIUC SP 2018โ15May 4, 2018Updated 8 years ago
- A cloud-native, distributed uptime monitor written in Goโ15Mar 7, 2023Updated 3 years ago
- a lock free chase-lev deque for zigโ17Apr 14, 2020Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer โข AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Running ahead of memory latency - Part II projectโ10Jan 7, 2023Updated 3 years ago
- A Basic C++ RISC-V Emulatorโ19Dec 26, 2020Updated 5 years ago
- FPGA version of CORDIC algorithm that evaluates all the trigonometric and anti-trigonometric functions.โ25Nov 20, 2019Updated 6 years ago
- Branch predictor simulation framework for the Last-Level Branch Predictorโ38Dec 3, 2025Updated 8 months ago
- ๐ LaTeX templates and tools for creating beautiful, structured documents ๐โ14Oct 24, 2025Updated 9 months ago
- CPU + xv6 + compilerโ18Feb 7, 2018Updated 8 years ago
- A LRU cache Implementation in Cโ21Oct 4, 2024Updated last year
- ็จRust่ฏญ่จ้ๆฐ่ฎพ่ฎกไธๅฎ็ฐxv6โ35Mar 7, 2022Updated 4 years ago
- Verilog implementation of the ASCON lightweight authenticated encryption and hashing algorithmโ10Nov 27, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer โข AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- XDMA PCIe to DDR4 and GPIO and BRAM for the Innova-2 Flex XCKU15P FPGAโ22Mar 7, 2024Updated 2 years ago
- Dual-core 16-bit RISC processorโ12Jul 21, 2024Updated 2 years ago
- Embecosm Software Package 1: Example SystemC loosely timed TLM 2.0 modelsโ18Sep 17, 2013Updated 12 years ago
- โ16Jan 14, 2022Updated 4 years ago
- rustsbi ๅผๅๆ็จโ41Mar 6, 2023Updated 3 years ago
- Works in Progress and Experiments for the Innova-2 Flex XCKU15P-based Boardโ18Apr 4, 2024Updated 2 years ago
- Wishbone to ARM AMBA 4 AXIโ17May 25, 2019Updated 7 years ago