saivittalb / branch-prediction-programming

Related projects ⓘ

Alternatives and complementary repositories for branch-prediction-programming

• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆47Updated 2 years ago
• RoyanTuscano / -TAGE-based-Predictor-Verilog-Code
  Verilog Implementation of TAGE based predictor by Andre Seznec and Pierre Michaud
  ☆15Updated 6 years ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆45Updated 11 months ago
• wshenyi / EECS-470-FinalProject
  A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.
  ☆9Updated 2 years ago
• baichen318 / arch-explorer
  ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis
  ☆30Updated 9 months ago
• lshpku / gem5-runahead
  Implementing the Precise Runahead (HPCA'20) in gem5
  ☆11Updated last year
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆49Updated 10 months ago
• epfl-vlsc / parendi
  Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU
  ☆17Updated 7 months ago
• CMU-SAFARI / Virtuoso
  Virtuoso is a new simulator that focuses on modelling various memory management and virtual memory aspects.
  ☆25Updated last year
• schoeberl / chisel-empty
  An almost empty chisel project as a starting point for hardware design
  ☆29Updated last year
• kevinliutong / chiselmill
  ☆10Updated 2 years ago
• yonseicasl / NPUsim
  NPUsim: Full-system, Cycle-accurate, Value-aware NPU Simulator
  ☆24Updated last week
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆34Updated 5 months ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated 5 months ago
• OpenXiangShan / GEM5
  ☆65Updated this week
• lizhirui / DreamCoreV2
  ☆20Updated last year
• GramThanos / CPU-on-Vivado-HLS
  A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS
  ☆18Updated 5 years ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated 8 months ago
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆24Updated 3 months ago
• qiyancos / gem5-with-chinese-comment
  Gem5 with chinese comment and introduction (master) and some other std gem5 version.
  ☆41Updated 2 years ago
• OpenXiangShan / xfuzz
  Fuzzing General-Purpose Hardware Designs with Software Fuzzers
  ☆11Updated 2 weeks ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆43Updated 2 weeks ago
• pku-liang / ksim
  ☆36Updated 7 months ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆60Updated this week
• CMU-SAFARI / PiDRAM
  PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …
  ☆59Updated 11 months ago
• miaochenlu / Gem5_tutorials
  ☆17Updated last year
• NSCSCC-2022-TJU / ChiselMIPS
  第六届龙芯杯混元形意太极门战队作品
  ☆16Updated 2 years ago
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆45Updated 10 months ago
• hplp / PiMulator
  Processing in Memory Emulation
  ☆18Updated last year
• pulp-platform / fpu
  ☆37Updated 5 years ago