Alternatives and similar repositories for vivado-docker

Users that are interested in vivado-docker are comparing it to the libraries listed below

• dramforever / ixayoi
  (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog
  ☆12Updated 3 years ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆63Updated 3 years ago
• chipsalliance / chisel-nix
  Nix template for the chisel-based industrial designing flows.
  ☆45Updated 4 months ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 8 months ago
• cyyself / cyyrv64
  My RV64 CPU (Work in progress)
  ☆19Updated 2 years ago
• jiegec / verilog-lang
  A hand-written recursive decent Verilog parser.
  ☆11Updated 2 years ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• sequencer / zaozi
  A eDSL framework based on Scala and MLIR, focusing on the Hardware design.
  ☆48Updated this week
• CircuitCoder / ChannelOS
  What if everything is a io_uring?
  ☆16Updated 2 years ago
• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆31Updated this week
• OpenRigil / openrigil-rtl
  Open-source RISC-V cryptographic hardware token, RTL repo
  ☆19Updated 2 years ago
• chipsalliance / playground
  chipyard in mill :P
  ☆78Updated last year
• dramforever / opensbi-h
  [No longer active] A fork of OpenSBI, with software-emulated hypervisor extension support
  ☆41Updated last week
• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆12Updated last year
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆21Updated 5 months ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆33Updated last year
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆46Updated last week
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆40Updated last year
• thu-cs-lab / JieLabs-Web
  Backend & Frontend for JieLabs
  ☆22Updated 2 years ago
• riscv / riscv-control-transfer-records
  This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…
  ☆23Updated 6 months ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆49Updated 9 months ago
• chipsalliance / espresso
  ☆40Updated 2 months ago
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆37Updated last year
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago
• jiegec / cpu
  Microarchitecture diagrams of several CPUs
  ☆37Updated last month
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• iscas-tis / chisel-formal-verification
  Formal verification tools for Chisel and RISC-V
  ☆13Updated last year
• cyyself / cemu
  A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …
  ☆117Updated 9 months ago
• cnrv / RVWC2021-slides
  第一届 RISC-V 中国峰会的幻灯片等资料存放
  ☆38Updated 2 years ago
• nju-mips / noop-lo
  A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.
  ☆29Updated 5 years ago