umd-memsys / DRAMSim2
DRAMSim2: A cycle accurate DRAM simulator
☆265Updated 4 years ago
Alternatives and similar repositories for DRAMSim2:
Users that are interested in DRAMSim2 are comparing it to the libraries listed below
- DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator☆357Updated 7 months ago
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆230Updated 2 years ago
- An integrated power, area, and timing modeling framework for multicore and manycore architectures☆180Updated 4 years ago
- A fast and flexible simulation infrastructure for exploring general-purpose processing-in-memory (PIM) architectures. Ramulator-PIM combi…☆156Updated 2 years ago
- Fast and accurate DRAM power and energy estimation tool☆152Updated last week
- A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, …☆624Updated last year
- An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model☆439Updated 9 months ago
- A pre-RTL, power-performance model for fixed-function accelerators☆174Updated last year
- PIMSim is a Process-In-Memory Simulator with the compatibility of GEM5 full-system simulation.☆195Updated last year
- Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and …☆306Updated 3 months ago
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆252Updated last week
- BookSim 2.0☆313Updated 9 months ago
- SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. T…☆130Updated last year
- Official repository of the Arm Research Starter Kit on System Modeling using gem5☆114Updated last year
- gem5 Tips & Tricks☆67Updated 5 years ago
- A fast and scalable x86-64 multicore simulator☆351Updated last year
- PrIM (Processing-In-Memory benchmarks) is the first benchmark suite for a real-world processing-in-memory (PIM) architecture. PrIM is dev…☆153Updated 10 months ago
- A heterogeneous architecture timing model simulator.☆150Updated 3 months ago
- Learning gem5 is a work-in-progress book to help gem5 users get started using gem5.☆180Updated 2 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆120Updated 4 years ago
- Comment on the rocket-chip source code☆177Updated 6 years ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆265Updated 4 months ago
- Processing-In-Memory (PIM) Simulator☆154Updated 3 months ago
- DAMOV is a benchmark suite and a methodical framework targeting the study of data movement bottlenecks in modern applications. It is inte…☆81Updated last year
- AutoSA: Polyhedral-Based Systolic Array Compiler☆215Updated 2 years ago
- Network on Chip Simulator☆262Updated last year
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆150Updated last year
- Joint HPS and ETH Repository to work towards open sourcing Scarab and Ramulator☆75Updated 10 months ago
- A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…☆72Updated 6 months ago
- Virtual Platform for NVDLA☆142Updated 6 years ago