In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.
☆126Feb 22, 2024Updated 2 years ago
Alternatives and similar repositories for Cadence-RTL-to-GDSII-Flow
Users that are interested in Cadence-RTL-to-GDSII-Flow are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RTL to GDS via Cadence Tools☆19May 17, 2022Updated 4 years ago
- Complete installation flow of yosys, OpenSTA and OpenROAD for RTL Verification, Synthesis, Timing Analysis, Power Analysis & GDSII layout…☆26Jul 21, 2025Updated last year
- ☆31Feb 22, 2024Updated 2 years ago
- Project of an integrated UART: RTL, Verification, Physical Implementation (Innovus) and GDSII.☆20May 28, 2021Updated 5 years ago
- The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a c…☆541Jul 18, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆18Dec 13, 2022Updated 3 years ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 4 years ago
- Example of a full DC synthesis script for a simple design☆14Feb 25, 2019Updated 7 years ago
- DTMF Receiver: Logic Synthesis and Physical Design using genus and innovus in 90nm process node☆18Dec 1, 2023Updated 2 years ago
- TCL, verilog and shell scripts used while learning Cadence genus, innovus and tempus tools.☆17Oct 24, 2021Updated 4 years ago
- This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specificatio…☆36Jan 23, 2024Updated 2 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆86May 2, 2021Updated 5 years ago
- This repo contains the skeleton scripts for running a full RTL2GDS flow using Cadence tools, as demonstrated in the Full RTL2GDS Demo pre…☆83Oct 18, 2025Updated 9 months ago
- This repository contains all the materials related to the basic MOSFET theory, CMOS technology, circuit and layout design, and basic PDK …☆15Dec 15, 2023Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆16May 23, 2024Updated 2 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆51Dec 3, 2023Updated 2 years ago
- The project involves the design of a 4X4 (16-bit) SRAM Memory Array using Cadence Virtuoso☆64Mar 21, 2024Updated 2 years ago
- Innovus backend scripts☆15Jun 20, 2022Updated 4 years ago
- ☆49Apr 7, 2024Updated 2 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆39Jun 2, 2021Updated 5 years ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆30Apr 29, 2024Updated 2 years ago
- cadence flow for genus and innovus with UPF added.☆17Jul 3, 2021Updated 5 years ago
- This project was done as a part of Beginner VLSI/SoC Physical design using open-source EDA Tools workshop.☆14Nov 23, 2020Updated 5 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- This repository contains the design files of RISC-V Single Cycle Core☆85Dec 14, 2023Updated 2 years ago
- ☆42Jun 24, 2026Updated last month
- Various low power labs using sky130☆13Sep 3, 2021Updated 4 years ago
- # 3.Interview_Questions In my experience, the questions i faced in the interviews and the people surrounded me must have faced a couple o…☆26Jul 9, 2025Updated last year
- 大三上做的本科毕设，包含BNN的替代梯度训练，verilog电路实现，完成180nm工艺流片。☆26Jun 30, 2025Updated last year
- ASIC implementation flow infrastructure, successor to OpenLane☆490Updated this week
- OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/☆693Updated this week
- Physical Design Flow from RTL to GDS using Opensource tools.☆131Nov 23, 2020Updated 5 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆84Nov 26, 2020Updated 5 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- To develop Arm Cortex-M0 based SoCs, from creating high-level functional specifications to design, implementation and testing on FPGA pla…☆42Dec 24, 2020Updated 5 years ago
- EE 287 2012 Fall☆34Mar 11, 2013Updated 13 years ago
- ☆15Jun 28, 2021Updated 5 years ago
- A 10bit SAR ADC in Sky130☆40Dec 4, 2022Updated 3 years ago
- 12 bit SAR ADC IP in Skywater 130 nm PDK☆31May 30, 2024Updated 2 years ago
- RTL blocks compatible with the Rocket Chip Generator☆17Mar 30, 2025Updated last year
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆36Feb 7, 2025Updated last year