yuankong11 / MIPS_CPUView external linksLinks
一个支持AXI总线、支持Cache、包括所有非浮点MIPS 1指令、支持例外的静态五级流水MIPS CPU
☆11Oct 8, 2019Updated 6 years ago
Alternatives and similar repositories for MIPS_CPU
Users that are interested in MIPS_CPU are comparing it to the libraries listed below
Sorting:
- ☆10Dec 15, 2023Updated 2 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆14Dec 23, 2022Updated 3 years ago
- Hardware and software implementation of Sparsely-active SNNs☆21Jan 9, 2025Updated last year
- verilog/FPGA hardware description for very simple GPU☆16Apr 9, 2019Updated 6 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆20Dec 8, 2012Updated 13 years ago
- verification of simple axi-based cache☆18May 14, 2019Updated 6 years ago
- A MCU implementation based PODES-M0O☆19Jan 31, 2020Updated 6 years ago
- Pipelined FFT/IFFT 256 points processor☆10Jul 17, 2014Updated 11 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆13Mar 26, 2024Updated last year
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆26Aug 28, 2016Updated 9 years ago
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆14Jan 4, 2019Updated 7 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆11Jun 3, 2019Updated 6 years ago
- 基于易灵思Ti60F225开发板和MT9M001双目摄像头，使用Verilog语言完成的双目拼接项目。摄像头输入图像数据后，在使用FAST计算图像特征点的同时，构建滑动窗口计算图像各个像素点的BRIEF描述符，完成后根据BRIEF描述符对两幅图像上的特征点进行暴力匹配，最后…☆20Apr 16, 2025Updated 9 months ago
- ☆38Aug 12, 2015Updated 10 years ago
- ☆11May 8, 2022Updated 3 years ago
- MAC system with IEEE754 compatibility☆13Nov 22, 2023Updated 2 years ago
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆11Aug 26, 2024Updated last year
- The second Homework of NLP☆13Jun 9, 2021Updated 4 years ago
- Single RISC-V CPU attached on AMBA AHB with Instruction and Data memories.☆13Oct 31, 2021Updated 4 years ago
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- A custom 16-bit computer☆12Oct 17, 2018Updated 7 years ago
- Implementation of a Systolic Array based sorting engine on an FPGA using Verilog☆11May 11, 2017Updated 8 years ago
- Network on chip based neural network accelerator☆10Mar 25, 2021Updated 4 years ago
- Density test bench for RISCV - "Compress extension"☆15Jun 21, 2021Updated 4 years ago
- 大三上做的本科毕设，包含BNN的替代梯度训练，verilog电路实现，完成180nm工艺流片。☆21Jun 30, 2025Updated 7 months ago
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆13Oct 19, 2024Updated last year
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆11Jan 8, 2022Updated 4 years ago
- Verilog-Based-NoC-Simulator☆10May 4, 2016Updated 9 years ago
- An out-of-order, dual issueed RISC-V core and SOC, a working project.☆10Apr 24, 2023Updated 2 years ago
- A simple cycle-accurate DaDianNao simulator☆13Mar 27, 2019Updated 6 years ago
- Special Function Units (SFUs) are hardware accelerators, their implementation helps improve the performance of GPUs to process some of th…☆15Sep 21, 2025Updated 4 months ago
- An Example implementation of Open Source Graphics Accelerator, (A fixed point, fixed function pipeline GPU)☆76Jun 7, 2012Updated 13 years ago
- Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL☆15Mar 21, 2024Updated last year
- ☆12Nov 11, 2015Updated 10 years ago
- Hardware Division Units☆10Jul 17, 2014Updated 11 years ago
- The original code for SCARA: Scalable Graph Neural Networks with Feature-Oriented Optimization (VLDB 2022) and Scalable Decoupling Graph …☆13Mar 8, 2024Updated last year
- RISC-V CPU in SystemVerilog & Custom Migen-based SoC Generator☆10Dec 29, 2021Updated 4 years ago
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆13Nov 12, 2025Updated 3 months ago