This is a simple Risc-v core for software simulation on FPGA.
☆10Apr 9, 2022Updated 3 years ago
Alternatives and similar repositories for simple_riscv_soft_core
Users that are interested in simple_riscv_soft_core are comparing it to the libraries listed below
Sorting:
- 大三上做的本科毕设，包含BNN的替代梯度训练，verilog电路实现，完成180nm工艺流片。☆21Jun 30, 2025Updated 8 months ago
- A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.☆18Aug 27, 2025Updated 6 months ago
- 基于Risc-V的计 算机体系结构设计。一栈式打通riscv架构硬件模拟器、操作系统、应用层！☆19Nov 25, 2024Updated last year
- ☆10Jun 7, 2022Updated 3 years ago
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆26Mar 13, 2025Updated 11 months ago
- 计算机体系结构研讨课 2020秋季 UCAS 《CPU设计实战》 工程环境及 RTL 代码合集☆18Aug 11, 2021Updated 4 years ago
- ☆22Apr 16, 2023Updated 2 years ago
- ☆19Jan 2, 2026Updated 2 months ago
- LLMA = LLM + Arithmetic coder, which use LLM to do insane text data compression. LLMA=大模型+算术编码，它能使用LLM对文本数据进行暴力的压缩，达到极高的压缩率。☆22Nov 24, 2024Updated last year
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Feb 23, 2026Updated last week
- Template for project1 TPU☆23May 1, 2021Updated 4 years ago
- "aura" my super-scalar O3 cpu core☆25May 25, 2024Updated last year
- ☆27Jan 22, 2023Updated 3 years ago
- ☆12Aug 12, 2022Updated 3 years ago
- 中国科学院大学高级计算机体系结构课程作业：使用OpenROAD-flow完成RTL到GDS全流程☆30May 30, 2020Updated 5 years ago
- AI Chip project☆34Jul 14, 2021Updated 4 years ago
- 该文档是个人阅读学习蜂鸟E203源码的笔记☆13Aug 1, 2023Updated 2 years ago
- 基于易灵思Ti60F225开发板和MT9M001双目摄像头，使用Verilog语言完成的双目拼接项目。摄像头输入图像数据后，在使用FAST计算图像特征点的同时，构建滑动窗口计算图像各个像素点的BRIEF描述符，完成后根据BRIEF描述符对两幅图像上的特征点进行暴力匹配，最后…☆20Apr 16, 2025Updated 10 months ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Feb 6, 2024Updated 2 years ago
- ☆38Jun 3, 2024Updated last year
- Alpha64 R10000 Two-Way Superscalar Processor☆11May 6, 2019Updated 6 years ago
- Simulator for a superscalar processor with dynamic scheduling and branch prediction☆15Nov 23, 2018Updated 7 years ago
- 基于FPGA的FFT算法并行优化☆13Mar 7, 2024Updated 2 years ago
- 2019年全国大学生电子设计大赛G题双路语音调频接收机的FPGA全实现☆17Apr 15, 2020Updated 5 years ago
- ☆93Sep 30, 2025Updated 5 months ago
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆12Aug 26, 2024Updated last year
- 经典的嵌入式OS - ucos-II 2.52版本全注释，仅供学习交流使用。☆12Oct 16, 2019Updated 6 years ago
- 算法第四版C++实现☆35Mar 2, 2018Updated 8 years ago
- FPGA Labs for EECS 151/251A (Fall 2021)☆11Oct 20, 2021Updated 4 years ago
- RISCV CPU implementation tutorial steps for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga☆15Updated this week
- ebhttps是首款基于eBPF革命性技术的开源web应用防火墙，最大的优点是零配置、不需要导入SSL证书、不中断生产环境等。☆12Jun 6, 2025Updated 9 months ago
- A Flexible Cache Architectural Simulator☆17Sep 16, 2025Updated 5 months ago
- A docker image for One Student One Chip's debug exam☆10Sep 22, 2023Updated 2 years ago
- Accelerate multihead attention transformer model using HLS for FPGA☆11Dec 7, 2023Updated 2 years ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆21Apr 25, 2025Updated 10 months ago
- ☆13May 8, 2025Updated 10 months ago
- Works for Applied Deep Learning / Machine Learning and Having It Deep and Structured (2017 FALL) @ NTU☆11Aug 14, 2018Updated 7 years ago
- ucas course information for students majoring in computer architecture.☆12Jul 7, 2024Updated last year
- Base on Synopsys platform using VCS,DC,ICC,PT.☆12May 29, 2021Updated 4 years ago