Alternatives and similar repositories for UCAS-Computer-Architecture-Lab:

Users that are interested in UCAS-Computer-Architecture-Lab are comparing it to the libraries listed below

• cebarobot / UCAS-CALab-mycpu_verify
  计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab3-Lab9
  ☆26Updated 3 years ago
• Corle-hyz / UCAS-COD-Lab
  中国科学院大学(UCAS)2020年春季学期计算机组成原理实验课作业
  ☆14Updated 2 years ago
• fluctlight001 / cpu_for_nscscc2022_single
  2022年龙芯杯个人赛 单发射110M（含icache）
  ☆44Updated 2 years ago
• NSCSCC-2020-Fudan / FDU1.1-NSCSCC
  复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品
  ☆41Updated 4 years ago
• 15947470421 / digital_IC_experiment
  我设计了一些数字集成电路的教学实验，供大家学习~
  ☆19Updated 3 weeks ago
• fluctlight001 / nscscc2022_single_tools
  龙芯杯个人赛工具包（适用于个人赛的golden_trace工具）
  ☆48Updated 11 months ago
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆122Updated 7 months ago
• OSCPU / ysyxSoC
  ☆79Updated this week
• fluctlight001 / cpu_for_nscscc2020
  2020龙芯杯个人赛 简易双发射60M（含ibuffer）
  ☆34Updated 4 years ago
• spokeyjoe / LoongArchCPU
  A LoongArch pipeline CPU. Project of Computer Architecture Lab @UCAS.
  ☆19Updated 8 months ago
• iFuProcessor / iFuCore
  ☆15Updated 6 months ago
• EricJin2002 / UCAS-CA-2022
  一个单发射五级静态流水CPU，采用龙芯32位精简版指令集，支持异常和中断处理，使用AXI总线接口，已集成TLB模块
  ☆14Updated 2 years ago
• OSCPU / yosys-sta
  ☆53Updated last month
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated 8 months ago
• fluctlight001 / Generic-Cache-Module
  适用于龙芯杯团队赛入门选手的应急cache模块
  ☆21Updated 11 months ago
• wataru030-XIAOHEI / My-RISCV64-CORE-writing
  一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .
  ☆25Updated 2 years ago
• nicolaswilde / UCAS-Advanced-Computer-Architecture-OpenROAD-flow
  中国科学院大学高级计算机体系结构课程作业：使用OpenROAD-flow完成RTL到GDS全流程
  ☆24Updated 4 years ago
• HIT-MaRiver-mips / cpucore-mariver
  ☆32Updated last year
• Sevenqi7 / NSCSCC-2022
  2022龙芯杯个人赛三等奖作品
  ☆13Updated last year
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆28Updated 10 months ago
• Yawei-Ding / ysyx_riscv64_cpu
  ☆57Updated last year
• cquwei-cx / cpu20220108
  MIPS 57条指令五级流水线cpu (verilog实现+详细注释)
  ☆10Updated 3 years ago
• Clo91eaf / PUA-MIPS
  NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.
  ☆10Updated 10 months ago
• fuzhidai / CPU-Design-Based-on-RISC-V
  Development using Verilog programing language and Vivado IDE .
  ☆14Updated 5 years ago
• ysyx-ta / ysyx-summer-readings
  ☆61Updated 6 months ago
• huaihailv / UCAS-CS-experience
  国科大计算机系本科课程经验总结
  ☆14Updated 3 years ago
• OpenXiangShan / GEM5
  ☆74Updated this week
• zencove-thu / zencove-zoom
  Highly configurable out-of-order MIPS32 processor, capable of booting Linux.
  ☆38Updated last year
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆47Updated 2 years ago
• OSCPU / chisel-playground
  ☆59Updated last week